LPC1111FHN33/101,5 NXP Semiconductors, LPC1111FHN33/101,5 Datasheet - Page 25
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LPC1111FHN33/101,5
Manufacturer Part Number
LPC1111FHN33/101,5
Description
IC MCU 32BIT 8KB FLASH 33HVQFN
Manufacturer
NXP Semiconductors
Series
LPC1100r
Datasheets
1.LPC1114FHN333015.pdf
(2 pages)
2.LPC1114FHN333015.pdf
(66 pages)
3.LPC1114FHN333015.pdf
(66 pages)
Specifications of LPC1111FHN33/101,5
Program Memory Type
FLASH
Program Memory Size
8KB (8K x 8)
Package / Case
33-VQFN Exposed Pad, 33-HVQFN, 33-SQFN, 33-DHVQFN
Core Processor
ARM Cortex-M0
Core Size
32-Bit
Speed
50MHz
Connectivity
I²C, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, POR, WDT
Number Of I /o
28
Ram Size
2K x 8
Voltage - Supply (vcc/vdd)
1.8 V ~ 3.6 V
Data Converters
A/D 8x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Processor Series
LPC11
Core
ARM Cortex M0
Data Bus Width
32 bit
Data Ram Size
8 KB
Interface Type
I2C, SPI, UART
Number Of Programmable I/os
28
Operating Supply Voltage
1.8 V to 3.6 V
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
3rd Party Development Tools
MDK-ARM, RL-ARM, ULINK2
Minimum Operating Temperature
- 40 C
On-chip Adc
10 bit, 8 Channel
Package
33HVQFN EP
Device Core
ARM Cortex M0
Family Name
LPC1100
Maximum Speed
50 MHz
Number Of Timers
4
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
For Use With
622-1005 - USB IN-CIRCUIT PROG ARM7 LPC2K
Eeprom Size
-
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
Other names
568-4957
935290771551
935290771551
NXP Semiconductors
LPC1111_12_13_14
Product data sheet
7.14.1 Features
7.13 System tick timer
7.14 Watchdog timer
The ARM Cortex-M0 includes a system tick timer (SYSTICK) that is intended to generate
a dedicated SYSTICK exception at a fixed time interval (typically 10 ms).
The purpose of the watchdog is to reset the microcontroller within a selectable time
period.
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Counter or timer operation.
One capture channel per timer, that can take a snapshot of the timer value when an
input signal transitions. A capture event may also generate an interrupt.
Four match registers per timer that allow:
– Continuous operation with optional interrupt generation on match.
– Stop timer on match with optional interrupt generation.
– Reset timer on match with optional interrupt generation.
Up to four external outputs corresponding to match registers, with the following
capabilities:
– Set LOW on match.
– Set HIGH on match.
– Toggle on match.
– Do nothing on match.
Internally resets chip if not periodically reloaded.
Debug mode.
Enabled by software but requires a hardware reset or a watchdog reset/interrupt to be
disabled.
Incorrect/Incomplete feed sequence causes reset/interrupt if enabled.
Flag to indicate watchdog reset.
Programmable 24-bit timer with internal prescaler.
Selectable time period from (T
multiples of T
The Watchdog Clock (WDCLK) source can be selected from the Internal RC oscillator
(IRC), the Watchdog oscillator, or the main clock. This gives a wide range of potential
timing choices of Watchdog operation under different power reduction conditions. It
also provides the ability to run the WDT from an entirely internal source that is not
dependent on an external crystal and its associated components and wiring for
increased reliability.
All information provided in this document is subject to legal disclaimers.
cy(WDCLK)
Rev. 4 — 10 February 2011
× 4.
cy(WDCLK)
× 256 × 4) to (T
32-bit ARM Cortex-M0 microcontroller
LPC1111/12/13/14
cy(WDCLK)
× 2
© NXP B.V. 2011. All rights reserved.
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× 4) in
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