AT32UC3A0512-ALUT Atmel, AT32UC3A0512-ALUT Datasheet - Page 226
AT32UC3A0512-ALUT
Manufacturer Part Number
AT32UC3A0512-ALUT
Description
IC MCU AVR32 512KB FLASH 144LQFP
Manufacturer
Atmel
Series
AVR®32 UC3r
Specifications of AT32UC3A0512-ALUT
Core Processor
AVR
Core Size
32-Bit
Speed
66MHz
Connectivity
EBI/EMI, Ethernet, I²C, SPI, SSC, UART/USART, USB OTG
Peripherals
Brown-out Detect/Reset, POR, PWM, WDT
Number Of I /o
109
Program Memory Size
512KB (512K x 8)
Program Memory Type
FLASH
Ram Size
64K x 8
Voltage - Supply (vcc/vdd)
1.65 V ~ 1.95 V
Data Converters
A/D 8x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
144-LQFP
Package
144LQFP
Device Core
AVR32
Family Name
AT32
Maximum Speed
66 MHz
Operating Supply Voltage
1.8|3.3 V
Data Bus Width
32 Bit
Number Of Programmable I/os
69
Interface Type
Ethernet/I2S/JTAG/SPI/TWI/USART
Number Of Timers
3
Processor Series
AT32UC3x
Core
AVR32
Data Ram Size
64 KB
Maximum Clock Frequency
66 MHz
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
3rd Party Development Tools
EWAVR32, EWAVR32-BL, KSK-EVK1100-PL
Development Tools By Supplier
ATAVRDRAGON, ATSTK500, ATSTK600, ATAVRISP2, ATAVRONEKIT, ATEXTWIFI, ATEVK1100, ATEVK1105, ATAVRRZ600
Minimum Operating Temperature
- 40 C
For Use With
ATEVK1105 - KIT EVAL FOR AT32UC3A0ATAVRONEKIT - KIT AVR/AVR32 DEBUGGER/PROGRMMR770-1008 - ISP 4PORT ATMEL AVR32 MCU SPIATEVK1100 - KIT DEV/EVAL FOR AVR32 AT32UC3A
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Lead Free Status / Rohs Status
Details
Available stocks
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Manufacturer
Quantity
Price
Company:
Part Number:
AT32UC3A0512-ALUT
Manufacturer:
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Quantity:
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Figure 24-9. Master Read with One Data Byte
Figure 24-10. Master Read with Multiple Data Bytes
24.10.6
24.10.6.1
32058J-AVR32-04/11
TXCOMP
RXRDY
TWD
Internal Address
S
7-bit Slave Addressing
Write START Bit
DADR
RXRDY bit is set in the status register, a character has been received in the receive-holding reg-
ister (RHR). The RXRDY bit is reset when reading the RHR.
When a single data byte read is performed, with or without internal address (IADR), the START
and STOP bits must be set at the same time. See
performed, with or without IADR, the STOP bit must be set after the next-to-last data received.
See
RXRDY is used as Receive Ready for the PDC receive channel.
The TWI interface can perform various transfer formats: Transfers with 7-bit slave address
devices and 10-bit slave address devices.
When Addressing 7-bit slave devices, the internal address bytes are used to perform random
address (read or write) accesses to reach one or more data bytes, within a memory page loca-
tion in a serial memory, for example. When performing read operations with an internal address,
the TWI performs a write operation to set the internal address into the slave device, and then
switch to Master Receiver mode. Note that the second start condition (after sending the IADR) is
sometimes called “repeated start” (Sr) in I2C fully-compatible devices. See
Figure 24-11
The three internal address bytes are configurable through the Master Mode register (MMR).
TXCOMP
RXRDY
R
Figure
TWD
A
24-10. For Internal Address usage see
and
S
DATA n
Write START &
Figure 24.11
STOP Bit
DADR
Read RHR
A
DATA n
for Master Write operation with internal address.
DATA (n+1)
R
A
A
DATA (n+1)
Read RHR
DATA
DATA (n+m)-1
Figure
”Internal Address” on page
Read RHR
N
24-9. When a multiple data byte read is
DATA (n+m)-1
P
A
Read RHR
after next-to-last data read
DATA (n+m)
Write STOP Bit
AT32UC3A
Figure
226.
N
24-12. See
DATA (n+m)
Read RHR
P
226
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