ATMEGA1281-16MU Atmel, ATMEGA1281-16MU Datasheet - Page 88

• Manufacturer Part Number: ATMEGA1281-16MU
• Description: IC MCU AVR 128K FLASH 64-QFN
• Manufacturer: Atmel
• Series: AVR® ATmegar

Specifications of ATMEGA1281-16MU

• Core Processor: AVR
• Core Size: 8-Bit
• Speed: 16MHz
• Connectivity: EBI/EMI, I²C, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, POR, PWM, WDT
• Number Of I /o: 54
• Program Memory Size: 128KB (64K x 16)
• Program Memory Type: FLASH
• Eeprom Size: 4K x 8
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 5.5 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 64-MLF®, 64-QFN
• Processor Series: ATMEGA128x
• Core: AVR8
• Data Bus Width: 8 bit
• Data Ram Size: 8 KB
• Interface Type: 2-Wire, SPI, UART
• Maximum Clock Frequency: 16 MHz
• Number Of Programmable I/os: 54
• Number Of Timers: 6
• Operating Supply Voltage: 4.5 V to 5.5 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: EWAVR, EWAVR-BL
• Development Tools By Supplier: ATAVRDRAGON, ATSTK500, ATSTK600, ATAVRISP2, ATAVRONEKIT, ATAVRRZ541, ATAVRRAVEN, ATAVRRZRAVEN, ATAVRRZUSBSTICK, ATAVRISP2, ATAVRRZ201
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 10 bit, 8 channel
• For Use With: ATSTK600-TQFP64 - STK600 SOCKET/ADAPTER 64-TQFPATAVRDB101 - MODULE DISPLAY LCD/RGB BACKLIGHT770-1007 - ISP 4PORT ATMEL AVR MCU SPI/JTAGATAVRISP2 - PROGRAMMER AVR IN SYSTEMATJTAGICE2 - AVR ON-CHIP D-BUG SYSTEM
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

2549M–AVR–09/10
Table 12-16. Overriding Signals for Alternate Functions PE7:PE4
Table 12-17. Overriding Signals for Alternate Functions in PE3:PE0
Note:
DIEOE
DIEOV
Signal
PUOE
PUOV
DDOE
DDOV
DIEOE
DIEOV
Name
PVOE
PVOV
Signal
DDOE
PUOE
PUOV
DDOV
Name
PVOE
PVOV
AIO
PE0
AIO
DI
DI
1. PDO/PDI only available at PE1/PE0 for
INT7 INPUT/ICP3
PE3/AIN1/OC3A
OC3B ENABLE
PE7/INT7/ICP3
INT7 ENABLE
AIN1 INPUT
INPUT
OC3B
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
–
ATmega640/1280/1281/2560/2561
PE2/AIN0/XCK0
XCK0 OUTPUT
XCK0 OUTPUT
XCK0 OUTPUT
INT7 INPUT/T3
XCK0 INPUT
AIN0 INPUT
INT6 ENABLE
PE6/INT6/T3
ENABLE
ENABLE
INPUT
0
1
0
0
0
0
0
0
0
0
0
0
1
–
ATmega1281/2561
PE5/INT5/OC3C
OC3C ENABLE
PE1/PDO
INT5 ENABLE
INT5 INPUT
TXEN0
TXEN0
TXEN0
TXD0
TXD0
OC3C
0
1
0
0
–
0
–
0
0
0
0
1
–
.
(1)
/
PCINT8 • PCIE1
PORTE0 • PUD
PCINT8 INPUT
PE4/INT4/OC3B
RXD0/PCINT8
OC3B ENABLE
INT4 ENABLE
PE0/PDI
INT4 INPUT
RXEN0
RXEN0
RXD0
OC3B
0
0
0
1
–
0
0
0
0
1
–
(1)
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