ATMEGA1281-16MU Atmel, ATMEGA1281-16MU Datasheet - Page 346
![IC MCU AVR 128K FLASH 64-QFN](/photos/12/13/121326/313-64-qfn_sml.jpg)
ATMEGA1281-16MU
Manufacturer Part Number
ATMEGA1281-16MU
Description
IC MCU AVR 128K FLASH 64-QFN
Manufacturer
Atmel
Series
AVR® ATmegar
Specifications of ATMEGA1281-16MU
Core Processor
AVR
Core Size
8-Bit
Speed
16MHz
Connectivity
EBI/EMI, I²C, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, POR, PWM, WDT
Number Of I /o
54
Program Memory Size
128KB (64K x 16)
Program Memory Type
FLASH
Eeprom Size
4K x 8
Ram Size
8K x 8
Voltage - Supply (vcc/vdd)
2.7 V ~ 5.5 V
Data Converters
A/D 8x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
64-MLF®, 64-QFN
Processor Series
ATMEGA128x
Core
AVR8
Data Bus Width
8 bit
Data Ram Size
8 KB
Interface Type
2-Wire, SPI, UART
Maximum Clock Frequency
16 MHz
Number Of Programmable I/os
54
Number Of Timers
6
Operating Supply Voltage
4.5 V to 5.5 V
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
3rd Party Development Tools
EWAVR, EWAVR-BL
Development Tools By Supplier
ATAVRDRAGON, ATSTK500, ATSTK600, ATAVRISP2, ATAVRONEKIT, ATAVRRZ541, ATAVRRAVEN, ATAVRRZRAVEN, ATAVRRZUSBSTICK, ATAVRISP2, ATAVRRZ201
Minimum Operating Temperature
- 40 C
On-chip Adc
10 bit, 8 channel
For Use With
ATSTK600-TQFP64 - STK600 SOCKET/ADAPTER 64-TQFPATAVRDB101 - MODULE DISPLAY LCD/RGB BACKLIGHT770-1007 - ISP 4PORT ATMEL AVR MCU SPI/JTAGATAVRISP2 - PROGRAMMER AVR IN SYSTEMATJTAGICE2 - AVR ON-CHIP D-BUG SYSTEM
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
- Current page: 346 of 444
- Download datasheet (10Mb)
29.7.11
29.7.12
2549M–AVR–09/10
Programming the Lock Bits
Reading the Fuse and Lock Bits
Figure 29-5. Programming the FUSES Waveforms
The algorithm for programming the Lock bits is as follows (refer to
page 341
1. A: Load Command “0010 0000”.
2. C: Load Data Low Byte. Bit n = “0” programs the Lock bit. If LB mode 3 is programmed
3. Give WR a negative pulse and wait for RDY/BSY to go high.
The Lock bits can only be cleared by executing Chip Erase.
The algorithm for reading the Fuse and Lock bits is as follows (refer to
on page 341
1. A: Load Command “0000 0100”.
2. Set OE to “0”, and BS2, BS1 to “00”. The status of the Fuse Low bits can now be read at
3. Set OE to “0”, and BS2, BS1 to “11”. The status of the Fuse High bits can now be read at
4. Set OE to “0”, and BS2, BS1 to “10”. The status of the Extended Fuse bits can now be
5. Set OE to “0”, and BS2, BS1 to “01”. The status of the Lock bits can now be read at DATA
6. Set OE to “1”.
(LB1 and LB2 is programmed), it is not possible to program the Boot Lock bits by any
External Programming mode.
DATA (“0” means programmed).
DATA (“0” means programmed).
read at DATA (“0” means programmed).
(“0” means programmed).
RESET +12V
RDY/BSY
PAGEL
XTAL1
DATA
for details on Command and Data loading):
XA1
XA0
BS1
BS2
WR
OE
for details on Command loading):
0x40
A
DATA
C
Write Fuse Low byte
XX
ATmega640/1280/1281/2560/2561
0x40
A
DATA
C
Write Fuse high byte
XX
“Programming the Flash” on
0x40
A
“Programming the Flash”
DATA
C
Write Extended Fuse byte
XX
346
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