PIC32MX795F512L-80I/PF Microchip Technology, PIC32MX795F512L-80I/PF Datasheet - Page 99
PIC32MX795F512L-80I/PF
Manufacturer Part Number
PIC32MX795F512L-80I/PF
Description
IC MCU 32BIT 512KB FLASH 100TQFP
Manufacturer
Microchip Technology
Series
PIC® 32MXr
Datasheets
1.PIC32MX320F032H-40IPT.pdf
(66 pages)
2.PIC32MX575F256H-80IMR.pdf
(2 pages)
3.PIC32MX575F256H-80IMR.pdf
(254 pages)
4.PIC32MX575F256H-80IMR.pdf
(14 pages)
5.PIC32MX575F256H-80IPT.pdf
(240 pages)
Specifications of PIC32MX795F512L-80I/PF
Core Size
32-Bit
Program Memory Size
512KB (512K x 8)
Core Processor
MIPS32® M4K™
Speed
80MHz
Connectivity
CAN, Ethernet, I²C, SPI, UART/USART, USB OTG
Peripherals
Brown-out Detect/Reset, DMA, POR, PWM, WDT
Number Of I /o
85
Program Memory Type
FLASH
Ram Size
128K x 8
Voltage - Supply (vcc/vdd)
2.3 V ~ 3.6 V
Data Converters
A/D 16x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
100-TQFP
Controller Family/series
PIC32
Ram Memory Size
128KB
Cpu Speed
80MHz
No. Of Timers
5
Interface
CAN, I2C, SPI, UART, USB
No. Of Pwm Channels
5
Embedded Interface Type
CAN, I2C, SPI, UART, USB
Rohs Compliant
Yes
Processor Series
PIC32MX7xx
Core
MIPS
3rd Party Development Tools
52713-733, 52714-737
Development Tools By Supplier
PG164130, DV164035, DV244005
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Lead Free Status / Rohs Status
Details
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
PIC32MX795F512L-80I/PF
Manufacturer:
TOSHIBA
Quantity:
4 600
Company:
Part Number:
PIC32MX795F512L-80I/PF
Manufacturer:
Microchip Technology
Quantity:
10 000
Part Number:
PIC32MX795F512L-80I/PF
Manufacturer:
MICROCHIP/微芯
Quantity:
20 000
TABLE 4-38:
TABLE 4-39:
Legend:
Note
Legend:
F200 DDPCON
7000
7010 PMMODE
7020 PMADDR
7030 PMDOUT
7040
7050
7060
1:
PMSTAT
PMCON
PMAEN
PMDIN
x = unknown value on Reset; — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
All registers in this table have corresponding CLR, SET and INV registers at their virtual addresses, plus offsets of 0x4, 0x8 and 0xC, respectively. See
information.
x = unknown value on Reset; — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
31:16
31:16
31:16
31:16
31:16
31:16
31:16
31:16
15:0
15:0
15:0
15:0 CS2EN/A15 CS1EN/A14
15:0
15:0
15:0
15:0
PARALLEL MASTER PORT REGISTER MAP
PROGRAMMING AND DIAGNOSTICS REGISTER MAP
31/15
BUSY
31/15
ON
IBF
—
—
—
—
—
—
—
30/14
30/14
IBOV
FRZ
—
—
—
—
—
—
—
IRQM<1:0>
29/13
29/13
SIDL
—
—
—
—
—
—
—
—
28/12
28/12
ADRMUX<1:0>
—
—
—
—
—
—
—
—
INCM<1:0>
27/11
27/11
IB3F
—
—
—
—
—
—
—
PMPTTL
MODE16
26/10
26/10
IB2F
—
—
—
—
—
—
—
(1)
PTWREN
25/9
25/9
IB1F
—
—
—
—
—
—
—
MODE<1:0>
PTRDEN
24/8
DATAOUT<31:0>
24/8
IB0F
DATAIN<31:0>
—
—
—
—
—
—
—
PTEN<15:0>
Bits
Bits
23/7
23/7
OBE
—
—
—
—
—
—
—
ADDR<13:0>
WAITB<1:0>
CSF<1:0>
OBUF
22/6
22/6
—
—
—
—
—
—
—
21/5
21/5
ALP
—
—
—
—
—
—
—
—
CS2P
20/4
20/4
—
—
—
—
—
—
—
—
Section 12.1.1 “CLR, SET and INV Registers”
WAITM<3:0>
JTAGEN
CS1P
OB3E
19/3
19/3
—
—
—
—
—
—
TROEN
OB2E
18/2
18/2
—
—
—
—
—
—
—
WRSP
OB1E
17/1
17/1
—
—
—
—
—
—
—
WAITE<1:0>
TDOEN
RDSP
OB0E
16/0
for more
16/0
—
—
—
—
—
—
0000
0008
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
008F