PIC32MX795F512L-80I/PF Microchip Technology, PIC32MX795F512L-80I/PF Datasheet - Page 67
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PIC32MX795F512L-80I/PF
Manufacturer Part Number
PIC32MX795F512L-80I/PF
Description
IC MCU 32BIT 512KB FLASH 100TQFP
Manufacturer
Microchip Technology
Series
PIC® 32MXr
Datasheets
1.PIC32MX320F032H-40IPT.pdf
(66 pages)
2.PIC32MX575F256H-80IMR.pdf
(2 pages)
3.PIC32MX575F256H-80IMR.pdf
(254 pages)
4.PIC32MX575F256H-80IMR.pdf
(14 pages)
5.PIC32MX575F256H-80IPT.pdf
(240 pages)
Specifications of PIC32MX795F512L-80I/PF
Core Size
32-Bit
Program Memory Size
512KB (512K x 8)
Core Processor
MIPS32® M4K™
Speed
80MHz
Connectivity
CAN, Ethernet, I²C, SPI, UART/USART, USB OTG
Peripherals
Brown-out Detect/Reset, DMA, POR, PWM, WDT
Number Of I /o
85
Program Memory Type
FLASH
Ram Size
128K x 8
Voltage - Supply (vcc/vdd)
2.3 V ~ 3.6 V
Data Converters
A/D 16x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
100-TQFP
Controller Family/series
PIC32
Ram Memory Size
128KB
Cpu Speed
80MHz
No. Of Timers
5
Interface
CAN, I2C, SPI, UART, USB
No. Of Pwm Channels
5
Embedded Interface Type
CAN, I2C, SPI, UART, USB
Rohs Compliant
Yes
Processor Series
PIC32MX7xx
Core
MIPS
3rd Party Development Tools
52713-733, 52714-737
Development Tools By Supplier
PG164130, DV164035, DV244005
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Lead Free Status / Rohs Status
Details
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
PIC32MX795F512L-80I/PF
Manufacturer:
TOSHIBA
Quantity:
4 600
Company:
Part Number:
PIC32MX795F512L-80I/PF
Manufacturer:
Microchip Technology
Quantity:
10 000
Part Number:
PIC32MX795F512L-80I/PF
Manufacturer:
MICROCHIP/微芯
Quantity:
20 000
TABLE 4-6:
Legend:
Note
10A0
10B0
10C0
1000 INTCON
1010 INTSTAT
1020
1030
1040
1050
1060
1070
1080
1090
1:
IPTMR
2:
IFS0
IFS1
IFS2
IEC0
IEC1
IEC2
IPC0
IPC1
IPC2
IPC3
x = unknown value on Reset; — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
All registers in this table have corresponding CLR, SET and INV registers at their virtual addresses, plus offsets of 0x4, 0x8 and 0xC, respectively. See
information.
These bits are not available on PIC32MX664 devices.
31:16
31:16
31:16
31:16
31:16
31:16
31:16
31:16
31:16
31:16
31:16
31:16
31:16
15:0
15:0
15:0
15:0
15:0
15:0
15:0
15:0
15:0
15:0
15:0
15:0
15:0
INTERRUPT REGISTER MAP FOR PIC32MX664F064L, PIC32MX664F128L, PIC32MX675F256L, PIC32MX675F512L AND
PIC32MX695F512L DEVICES
I2C1MIF
I2C1MIE
RTCCIF
RTCCIE
INT3IF
IC3EIF
INT3IE
IC3EIE
31/15
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
I2C1SIF
FSCMIF
I2C1SIE
FSCMIE
IC2EIF
IC2EIE
OC3IF
OC3IE
30/14
FRZ
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
I2C2MIF
I2C2MIE
I2C1BIF
I2C1BIE
IC1EIF
IC1EIE
29/13
IC3IF
IC3IE
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
SPI3TXIF SPI3RXIF
SPI3TXIE SPI3RXIE
I2C3MIF
I2C3MIE
I2C2SIF
U1TXIE
I2C2SIE
U1TXIF
MVEC
ETHIF
ETHIE
28/12
T3IF
T3IE
—
—
—
—
—
—
—
(1)
INT0IP<2:0>
INT1IP<2:0>
INT2IP<2:0>
INT3IP<2:0>
CS0IP<2:0>
IC1IP<2:0>
IC2IP<2:0>
IC3IP<2:0>
I2C3SIE
I2C2BIE
U1RXIF
I2C3SIF
I2C2BIF
U1RXIE
U5TXIE
U5TXIF
INT2IF
INT2IE
27/11
—
—
—
—
—
—
—
—
SPI4TXIE SPI4RXIE
SPI4TXIF SPI4RXIF
SPI3EIF
I2C5MIF
SPI3EIE
I2C3BIE
I2C5MIE
I2C3BIF
U2TXIF
U5RXIF
U2TXIE
U5RXIE
OC2IE
26/10
U1EIF
OC2IF
U1EIE
—
—
—
—
—
—
SRIPL<2:0>
TPC<2:0>
SPI1TXIE SPI1RXIE
SPI1TXIF SPI1RXIF
I2C5SIF
I2C5SIE
U2RXIF
U2RXIE
USBIF
USBIE
U5EIF
U5EIE
IC2IF
IC2IE
25/9
—
—
—
—
INT0IS<1:0>
INT1IS<1:0>
INT2IS<1:0>
INT3IS<1:0>
CS0IS<1:0>
IC1IS<1:0>
IC2IS<1:0>
IC3IS<1:0>
SPI4EIF
I2C5BIF
SPI4EIE
I2C5BIE
U6TXIF
U6TXIE
FCEIF
FCEIE
U2EIE
U2EIF
24/8
T2IF
T2IE
—
—
—
—
IPTMR<31:0>
Bits
DMA7IF
DMA7IE
SPI2TXIF SPI2RXIF
SPI2TXIE SPI2RXIE
I2C4MIF
I2C4MIE
SPI1EIF
SPI1EIE
U6RXIE
U3TXIF
U6RXIF
U3TXIE
INT1IE
INT1IF
23/7
—
—
—
—
—
—
—
—
—
—
—
—
—
—
(2)
(2)
DMA6IF
DMA6IE
U3RXIF
I2C4SIF
U3RXIE
I2C4SIE
OC5IF
OC1IF
U6EIF
OC5IE
OC1IE
U6EIE
22/6
—
—
—
—
—
—
—
—
—
—
—
—
—
—
(2)
(2)
DMA5IE
DMA5IF
SPI2EIF
SPI2EIE
I2C4BIE
I2C4BIF
U4TXIE
U4TXIF
U3EIF
U3EIE
IC5IF
IC1IF
IC5IE
IC1IE
21/5
—
—
—
—
—
—
—
—
—
—
—
—
—
(2)
(2)
DMA4IE
DMA4IF
CMP2IE
INT4EP
CMP2IF
U4RXIF
U4RXIE
20/4
T5IF
T1IF
T5IE
T1IE
—
—
—
—
Section 12.1.1 “CLR, SET and INV Registers”
(2)
(2)
CS1IP<2:0>
OC1IP<2:0>
OC2IP<2:0>
OC3IP<2:0>
CTIP<2:0>
T1IP<2:0>
T2IP<2:0>
T3IP<2:0>
DMA3IF
CMP1IF
DMA3IE
CMP1IE
INT3EP
INT4IF
INT0IF
INT4IE
INT0IE
U4EIF
U4EIE
19/3
—
—
—
—
VEC<5:0>
DMA2IF
PMPEIF
DMA2IE
PMPEIE
INT2EP
OC4IF
PMPIF
OC4IE
CS1IE
PMPIE
CS1IF
18/2
—
—
—
—
DMA1IF
DMA1IE
INT1EP
IC5EIF
IC5EIE
CS0IE
AD1IE
CS0IF
AD1IF
IC4IF
IC4IE
17/1
—
—
—
—
CS1IS<1:0>
OC1IS<1:0>
OC2IS<1:0>
OC3IS<1:0>
CTIS<1:0>
T1IS<1:0>
T2IS<1:0>
T3IS<1:0>
DMA0IF
DMA0IE
INT0EP
IC4EIF
IC4EIE
CNIF
CNIE
16/0
CTIF
T4IE
CTIE
SS0
T4IF
—
—
—
for more
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000