ATMEGA64L-8MQ Atmel, ATMEGA64L-8MQ Datasheet - Page 57
ATMEGA64L-8MQ
Manufacturer Part Number
ATMEGA64L-8MQ
Description
IC MCU AVR 64K FLASH 64-QFN
Manufacturer
Atmel
Series
AVR® ATmegar
Specifications of ATMEGA64L-8MQ
Core Processor
AVR
Core Size
8-Bit
Speed
8MHz
Connectivity
I²C, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, POR, PWM, WDT
Number Of I /o
53
Program Memory Size
64KB (32K x 16)
Program Memory Type
FLASH
Eeprom Size
2K x 8
Ram Size
4K x 8
Voltage - Supply (vcc/vdd)
2.7 V ~ 5.5 V
Data Converters
A/D 8x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
64-MLF®, 64-QFN
Processor Series
ATMEGA64x
Core
AVR8
Data Bus Width
8 bit
Data Ram Size
4 KB
Interface Type
2-Wire, JTAG, SPI, USART
Maximum Clock Frequency
8 MHz
Number Of Programmable I/os
53
Number Of Timers
4
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
3rd Party Development Tools
EWAVR, EWAVR-BL
Minimum Operating Temperature
- 40 C
On-chip Adc
10 bit, 8 Channel
For Use With
ATSTK600-TQFP64 - STK600 SOCKET/ADAPTER 64-TQFPATSTK600-TQFP32 - STK600 SOCKET/ADAPTER 32-TQFP770-1007 - ISP 4PORT ATMEL AVR MCU SPI/JTAGATAVRISP2 - PROGRAMMER AVR IN SYSTEMATJTAGICE2 - AVR ON-CHIP D-BUG SYSTEMATSTK500 - PROGRAMMER AVR STARTER KIT
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
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- Download datasheet (8Mb)
WDTCR – Watchdog
Timer Control Register
2490Q–AVR–06/10
Table 21. WDT Configuration as a Function of the Fuse Settings of M103C and WDTON
Figure 28. Watchdog Timer
• Bits 7..5 – Res: Reserved Bits
These bits are reserved bits in the ATmega64 and will always read as zero.
• Bit 4 – WDCE: Watchdog Change Enable
This bit must be set when the WDE bit is written to logic zero. Otherwise, the Watchdog will not
be disabled. Once written to one, hardware will clear this bit after four clock cycles. Refer to the
description of the WDE bit for a Watchdog disable procedure. In Safety Level 1 and 2, this bit
must also be set when changing the prescaler bits.
Configuration of the Watchdog Timer” on page 60.
• Bit 3 – WDE: Watchdog Enable
When the WDE is written to logic one, the Watchdog Timer is enabled, and if the WDE is written
to logic zero, the Watchdog Timer function is disabled. WDE can only be cleared if the WDCE bit
Bit
0x21 (0x41)
Read/Write
Initial Value
M103C
Unprogrammed
Unprogrammed
Programmed
Programmed
R
7
–
0
WDTON
Unprogrammed
Programmed
Unprogrammed
Programmed
OSCILLATOR
WATCHDOG
R
6
–
0
R
5
–
0
Safety
Level
1
2
0
2
WDCE
R/W
4
0
WDT
Initial
State
Disabled
Enabled
Disabled
Enabled
WDE
R/W
3
0
See “Timed Sequences for Changing the
WDP2
R/W
Timed
enabled
Timed
sequence
enabled
How to
Disable the
WDT
sequence
Always
Always
2
0
WDP1
R/W
1
0
ATmega64(L)
WDP0
R/W
How to
Change
Time-out
Timed
sequence
Timed
sequence
No restriction
Timed
sequence
0
0
WDTCR
57
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