ATMEGA64L-8MU Atmel, ATMEGA64L-8MU Datasheet - Page 23

• Manufacturer Part Number: ATMEGA64L-8MU
• Description: IC AVR MCU 64K 8MHZ 3V 64-QFN
• Manufacturer: Atmel
• Series: AVR® ATmegar

Specifications of ATMEGA64L-8MU

• Core Processor: AVR
• Core Size: 8-Bit
• Speed: 8MHz
• Connectivity: I²C, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, POR, PWM, WDT
• Number Of I /o: 53
• Program Memory Size: 64KB (32K x 16)
• Program Memory Type: FLASH
• Eeprom Size: 2K x 8
• Ram Size: 4K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 5.5 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 64-MLF®, 64-QFN
• Cpu Family: ATmega
• Device Core: AVR
• Device Core Size: 8b
• Frequency (max): 8MHz
• Interface Type: JTAG/SPI/TWI/USART
• Total Internal Ram Size: 4KB
• # I/os (max): 53
• Number Of Timers - General Purpose: 4
• Operating Supply Voltage (typ): 3.3/5V
• Operating Supply Voltage (max): 5.5V
• Operating Supply Voltage (min): 2.7V
• On-chip Adc: 8-chx10-bit
• Instruction Set Architecture: RISC
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 64
• Package Type: MLF EP
• Processor Series: ATMEGA64x
• Core: AVR8
• Data Bus Width: 8 bit
• Data Ram Size: 4 KB
• Maximum Clock Frequency: 8 MHz
• Number Of Programmable I/os: 53
• Number Of Timers: 4
• Operating Supply Voltage: 2.7 V to 5.5 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: EWAVR, EWAVR-BL
• Minimum Operating Temperature: - 40 C
• Package: 64MLF EP
• Family Name: ATmega
• Maximum Speed: 8 MHz
• Controller Family/series: AVR MEGA
• No. Of I/o's: 53
• Eeprom Memory Size: 2KB
• Ram Memory Size: 4KB
• Cpu Speed: 8MHz
• Rohs Compliant: Yes
• For Use With: ATSTK600-TQFP64 - STK600 SOCKET/ADAPTER 64-TQFPATSTK600-TQFP32 - STK600 SOCKET/ADAPTER 32-TQFP770-1007 - ISP 4PORT ATMEL AVR MCU SPI/JTAGATAVRISP2 - PROGRAMMER AVR IN SYSTEMATJTAGICE2 - AVR ON-CHIP D-BUG SYSTEMATSTK500 - PROGRAMMER AVR STARTER KIT
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Changes from Rev.
2490B-09/02 to
Rev. 2490C-09/02
Changes from Rev.
2490A-10/01 to
Rev. 2490B-09/02
2490QS–AVR–07/10
10. Added section
11. Changed V
12. Added information about conversion time for Differential mode with Auto Triggering
13. Added t
14. Updated
1. Changed the Endurance on the Flash to 10,000 Write/Erase Cycles.
1. Added 64-pad QFN/MLF Package and updated
2. Added the section
3. Added the section
4. Renamed SPMCR to SPMCSR in entire document.
5. Added Some Preliminary Test Limits and Characterization Data
6. Removed Alternative Algortihm for Leaving JTAG Programming Mode.
7. Improved description on how to do a polarity check of the ADC diff results in
8. Updated Programming Figures:
9. Added
10. Updated
11. Updated Description of OSCCAL Calibration Byte.
on
page
Removed some of the TBD's and corrected data in the following tables and pages:
Table 2 on page
12 on page
on page
327,
See “Leaving Programming Mode” on page 321.
Conversion Result” on page
Figure 138 on page 294
must be connected during Programming mode.
how to program the fuses.
“PROG_PAGEREAD (0x7)” instructions on
More details regarding use of the TWI Power-down operation and using the TWI as master
with low TWBRR values are added into the data sheet. Added the note at the end of the
Rate Generator Unit” on page
on page
page
Table 134 on page
35.
WD_FUSE
205.
56,
234.
“Packaging Information” on page
a
“TWI – Two-wire Serial Interface” on page
HYST
42,
Table 22 on page
note
Table 14 on page
“EEPROM Write During Power-down Sleep Mode” on page
value to 120 in
in
24,
Table 128 on page
“Default Clock Source” on page
“Using all Locations of External Memory Smaller than 64 KB” on
regarding
Table 7 on page
330,
and
Figure 147 on page 306
Table 136 on page
204. Added the description at the end of
242.
58,
Table 19 on page
usage
43,
“DC Characteristics” on page
Table 16 on page
38,
308.
Table 9 on page
of
16.
page
the
Figure 142 on page 301
333, and
“Ordering Information” on page
52.
313.
are updated to also reflect that AVCC
“PROG_PAGELOAD
39.
198.
44,
Table 137
41,
Table 19 on page
Table 10 on page
ATmega64(L)
325,
-
Table
“Address Match Unit”
Table 131 on page
added to illustrate
144.
(0x6)”
52,
25.
41,
Table 20
15.
“ADC
Table
and
“Bit
23