AT91SAM7X512-AU-999 Atmel, AT91SAM7X512-AU-999 Datasheet - Page 198
AT91SAM7X512-AU-999
Manufacturer Part Number
AT91SAM7X512-AU-999
Description
IC MCU ARM 512K HS FLASH 100LQFP
Manufacturer
Atmel
Series
AT91SAMr
Datasheet
1.AT91SAM7X512-AU-999.pdf
(687 pages)
Specifications of AT91SAM7X512-AU-999
Core Processor
ARM7
Core Size
16/32-Bit
Speed
55MHz
Connectivity
CAN, Ethernet, I²C, SPI, SSC, UART/USART, USB
Peripherals
Brown-out Detect/Reset, DMA, POR, PWM, WDT
Number Of I /o
62
Program Memory Size
512KB (512K x 8)
Program Memory Type
FLASH
Ram Size
128K x 8
Voltage - Supply (vcc/vdd)
1.65 V ~ 1.95 V
Data Converters
A/D 8x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
100-LQFP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
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25.9.9
Register Name:
Access Type:
Possible limitations on PLL input frequencies and multiplier factors should be checked before using the PMC.
• DIV: Divider
• PLLCOUNT: PLL Counter
Specifies the number of slow clock cycles before the LOCK bit is set in PMC_SR after CKGR_PLLR is written.
• OUT: PLL Clock Frequency Range
To optimize clock performance, this field must be programmed as specified in “PLL Characteristics” in the Electrical Char-
acteristics section of the product datasheet.
• MUL: PLL Multiplier
0 = The PLL is deactivated.
1 up to 2047 = The PLL Clock frequency is the PLL input frequency multiplied by MUL+ 1.
• USBDIV: Divider for USB Clock
198
DIV
0
1
2 - 255
31
23
15
–
7
0
0
1
1
AT91SAM7X512/256/128 Preliminary
PMC Clock Generator PLL Register
OUT
USBDIV
30
22
14
CKGR_PLLR
Read-write
–
6
0
1
0
1
29
21
13
5
USBDIV
Divider Selected
Divider output is 0
Divider is bypassed
Divider output is the selected clock divided by DIV.
Divider for USB Clock(s)
Divider output is PLL clock output.
Divider output is PLL clock output divided by 2.
Divider output is PLL clock output divided by 4.
Reserved.
28
20
12
4
MUL
DIV
27
19
11
3
–
PLLCOUNT
26
18
10
2
MUL
25
17
9
1
6120H–ATARM–17-Feb-09
24
16
8
0
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