AT89C51CC03UA-SLSUM Atmel, AT89C51CC03UA-SLSUM Datasheet - Page 9
AT89C51CC03UA-SLSUM
Manufacturer Part Number
AT89C51CC03UA-SLSUM
Description
IC 8051 MCU FLASH 64K 44PLCC
Manufacturer
Atmel
Series
AT89C CANr
Datasheet
1.AT89C51CC03C-S3RIM.pdf
(198 pages)
Specifications of AT89C51CC03UA-SLSUM
Core Processor
8051
Core Size
8-Bit
Speed
40MHz
Connectivity
CAN, UART/USART
Peripherals
POR, PWM, WDT
Number Of I /o
36
Program Memory Size
64KB (64K x 8)
Program Memory Type
FLASH
Eeprom Size
2K x 8
Ram Size
2.25K x 8
Voltage - Supply (vcc/vdd)
3 V ~ 5.5 V
Data Converters
A/D 8x10b
Oscillator Type
External
Operating Temperature
-40°C ~ 85°C
Package / Case
44-PLCC
Processor Series
AT89x
Core
8051
Data Bus Width
8 bit
Data Ram Size
2304 B
Interface Type
UART, SPI
Maximum Clock Frequency
60 MHz
Number Of Programmable I/os
36
Number Of Timers
2
Operating Supply Voltage
3 V to 5.5 V
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
3rd Party Development Tools
PK51, CA51, A51, ULINK2
Minimum Operating Temperature
- 40 C
On-chip Adc
10 bit, 8 Channel
For Use With
AT89OCD-01 - USB EMULATOR FOR AT8XC51 MCU
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Other names
AT89C51CC03UASLSUM
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Read-Modify-Write
Instructions
4182O–CAN–09/08
Figure 3. Port 2 Structure
Notes:
When Port 0 and Port 2 are used for an external memory cycle, an internal control signal
switches the output-driver input from the latch output to the internal address/data line.
Some instructions read the latch data rather than the pin data. The latch based instruc-
tions read the data, modify the data and then rewrite the latch. These are called "Read-
Modify-Write" instructions. Below is a complete list of these special instructions (see
Table ). When the destination operand is a Port or a Port bit, these instructions read the
latch rather than the pin:
It is not obvious the last three instructions in this list are Read-Modify-Write instructions.
These instructions read the port (all 8 bits), modify the specifically addressed bit and
MOV Px.y, C
Instruction
READ
LATCH
INTERNAL
BUS
CLR Px.y
WRITE
TO
LATCH
SET Px.y
READ
PIN
DJNZ
DEC
ORL
ANL
XRL
JBC
CPL
1. Port 2 is precluded from use as general-purpose I/O Ports when as address/data bus
2. Port 2 internal strong pull-ups FET (P1 in FiGURE) assist the logic-one output for
INC
drivers.
memory bus cycle.
Description
logical AND
logical OR
logical EX-OR
jump if bit = 1 and clear bit
complement bit
increment
decrement
decrement and jump if not zero
move carry bit to bit y of Port x
clear bit y of Port x
set bit y of Port x
D
LATCH
P2.X
ADDRESS HIGH/ CONTROL
Q
1
0
Example
ANL P1, A
ORL P2, A
XRL P3, A
JBC P1.1, LABEL
CPL P3.0
INC P2
DEC P2
DJNZ P3, LABEL
MOV P1.5, C
CLR P2.4
SET P3.3
AT89C51CC03
VDD
INTERNAL
PULL-UP (2)
P2.x (1)
9
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