AT89C51CC03UA-SLSUM Atmel, AT89C51CC03UA-SLSUM Datasheet - Page 118
AT89C51CC03UA-SLSUM
Manufacturer Part Number
AT89C51CC03UA-SLSUM
Description
IC 8051 MCU FLASH 64K 44PLCC
Manufacturer
Atmel
Series
AT89C CANr
Datasheet
1.AT89C51CC03C-S3RIM.pdf
(198 pages)
Specifications of AT89C51CC03UA-SLSUM
Core Processor
8051
Core Size
8-Bit
Speed
40MHz
Connectivity
CAN, UART/USART
Peripherals
POR, PWM, WDT
Number Of I /o
36
Program Memory Size
64KB (64K x 8)
Program Memory Type
FLASH
Eeprom Size
2K x 8
Ram Size
2.25K x 8
Voltage - Supply (vcc/vdd)
3 V ~ 5.5 V
Data Converters
A/D 8x10b
Oscillator Type
External
Operating Temperature
-40°C ~ 85°C
Package / Case
44-PLCC
Processor Series
AT89x
Core
8051
Data Bus Width
8 bit
Data Ram Size
2304 B
Interface Type
UART, SPI
Maximum Clock Frequency
60 MHz
Number Of Programmable I/os
36
Number Of Timers
2
Operating Supply Voltage
3 V to 5.5 V
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
3rd Party Development Tools
PK51, CA51, A51, ULINK2
Minimum Operating Temperature
- 40 C
On-chip Adc
10 bit, 8 Channel
For Use With
AT89OCD-01 - USB EMULATOR FOR AT8XC51 MCU
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Other names
AT89C51CC03UASLSUM
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AT89C51CC03
Table 65. CANSTCH Register
CANSTCH (S:B2h)
CAN Message Object Status Register
Note:
No default value after reset.
Number
DLCW
Bit
7
7
6
5
4
3
2
1
0
See Figure 50.
Bit Mnemonic Description
TXOK
DLCW
RXOK
BERR
SERR
CERR
AERR
TXOK
FERR
6
RXOK
Data Length Code Warning
The incoming message does not have the DLC expected. Whatever the frame
type, the DLC field of the CANCONCH register is updated by the received
DLC.
Transmit OK
The communication enabled by transmission is completed.
When the controller is ready to send a frame, if two or more message objects
are enabled as producers, the lower index message object (0 to 13) is
supplied first.
This flag can generate an interrupt.
Receive OK
The communication enabled by reception is completed.
In the case of two or more message object reception hits, the lower index
message object (0 to 13) is updated first.
This flag can generate an interrupt.
Bit Error (Only in Transmission)
The bit value monitored is different from the bit value sent.
Exceptions:
the monitored recessive bit sent as a dominant bit during the arbitration field
and the acknowledge slot detecting a dominant bit during the sending of an
error frame.
This flag can generate an interrupt.
Stuff Error
Detection of more than five consecutive bits with the same polarity.
This flag can generate an interrupt.
CRC Error
The receiver performs a CRC check on each destuffed received message
from the start of frame up to the data field.
If this checking does not match with the destuffed CRC field, a CRC error is
set.
This flag can generate an interrupt.
Form Error
The form error results from one or more violations of the fixed form in the
following bit fields:
CRC delimiter
acknowledgment delimiter
end_of_frame
This flag can generate an interrupt.
Acknowledgment Error
No detection of the dominant bit in the acknowledge slot.
This flag can generate an interrupt.
5
BERR
4
SERR
3
CERR
2
4182O–CAN–09/08
FERR
1
AERR
0
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