AT89C51CC03UA-SLSUM Atmel, AT89C51CC03UA-SLSUM Datasheet - Page 46
AT89C51CC03UA-SLSUM
Manufacturer Part Number
AT89C51CC03UA-SLSUM
Description
IC 8051 MCU FLASH 64K 44PLCC
Manufacturer
Atmel
Series
AT89C CANr
Datasheet
1.AT89C51CC03C-S3RIM.pdf
(198 pages)
Specifications of AT89C51CC03UA-SLSUM
Core Processor
8051
Core Size
8-Bit
Speed
40MHz
Connectivity
CAN, UART/USART
Peripherals
POR, PWM, WDT
Number Of I /o
36
Program Memory Size
64KB (64K x 8)
Program Memory Type
FLASH
Eeprom Size
2K x 8
Ram Size
2.25K x 8
Voltage - Supply (vcc/vdd)
3 V ~ 5.5 V
Data Converters
A/D 8x10b
Oscillator Type
External
Operating Temperature
-40°C ~ 85°C
Package / Case
44-PLCC
Processor Series
AT89x
Core
8051
Data Bus Width
8 bit
Data Ram Size
2304 B
Interface Type
UART, SPI
Maximum Clock Frequency
60 MHz
Number Of Programmable I/os
36
Number Of Timers
2
Operating Supply Voltage
3 V to 5.5 V
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
3rd Party Development Tools
PK51, CA51, A51, ULINK2
Minimum Operating Temperature
- 40 C
On-chip Adc
10 bit, 8 Channel
For Use With
AT89OCD-01 - USB EMULATOR FOR AT8XC51 MCU
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Other names
AT89C51CC03UASLSUM
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Overview of FM0
Operations
Flash Registers (SFR)
FCON Register
46
AT89C51CC03
The CPU interfaces to the flash memory through the FCON register, AUXR1 register
and FSTA register.
These registers are used to map the column latches, HSB, extra row and EEDATA in
the working data or code space.
Table 13. FCON Register
FCON Register (S:D1h)
Flash Control Register
Reset Value= 0000 0000b
Number
FPL3
Bit
7-4
2-1
7
3
0
Mnemonic Description
FMOD1:0
FBUSY
FPL3:0
FPL2
FPS
Bit
6
Programming Launch Command Bits
Write 5Xh followed by AXh to launch the programming according to FMOD1:0.
(see Table 16.)
Flash Map Program Space
When this bit is set:
The MOVX @DPTR, A instruction writes in the columns latches space
When this bit is cleared:
The MOVX @DPTR, A instruction writes in the regular XDATA memory space
Flash Mode
See Table 16.
Flash Busy
Set by hardware when programming is in progress.
Clear by hardware when programming is done.
Can not be changed by software.
FPL1
5
FPL0
4
FPS
3
FMOD1
2
4182O–CAN–09/08
FMOD0
1
FBUSY
0
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