AT89C5122D-RDTUM Atmel, AT89C5122D-RDTUM Datasheet - Page 136
![IC 8051 MCU FLASH 32K 64VQFP](/photos/6/81/68127/313-64-vqfp_sml.jpg)
AT89C5122D-RDTUM
Manufacturer Part Number
AT89C5122D-RDTUM
Description
IC 8051 MCU FLASH 32K 64VQFP
Manufacturer
Atmel
Series
89Cr
Datasheet
1.AT89C5122D-PSTUM.pdf
(208 pages)
Specifications of AT89C5122D-RDTUM
Core Processor
8051
Core Size
8-Bit
Speed
48MHz
Connectivity
SmartCard, SPI, UART/USART, USB
Peripherals
LED, POR, WDT
Number Of I /o
46
Program Memory Size
32KB (32K x 8)
Program Memory Type
FLASH
Ram Size
768 x 8
Voltage - Supply (vcc/vdd)
3 V ~ 5.5 V
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
64-TQFP, 64-VQFP
For Use With
AT89OCD-01 - USB EMULATOR FOR AT8XC51 MCUAT89STK-10 - KIT EVAL APPL MASS STORAGEAT89STK-03 - KIT STARTER FOR MCU AT8XC5122/23
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Data Converters
-
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Slave Select (SS)
Baud Rate
136
AT83R5122, AT8xC5122/23
Each Slave peripheral is selected by one Slave Select pin (SS). This signal must stay
low for any message for a Slave. Only one Master (SS high level) can drive the network.
The Master may select each Slave device by software through port pins (Figure 82). To
prevent bus conflicts on the MISO line, only one slave should be selected at a time by
the Master for a transmission.
In a Master configuration, the SS line can be used in conjunction with the MODF flag in
the SPI Status register (SPSTA) to prevent multiple masters from driving MOSI and
SCK (see Section “Error Conditions”, page 140).
A high level on the SS pin puts the MISO line of a Slave SPI in a high-impedance state.
The SS pin could be used as a general-purpose if the following conditions are met:
•
•
In Master mode, the baud rate can be selected from a baud rate generator which is con-
troled by three bits in the SPCON register: SPR2, SPR1 and SPR0. The Master clock is
chosen from one of six clock rates resulting from the division of the internal clock by 4, 8,
16, 32, 64 or 128.
Table 83 gives the different clock rates selected by SPR2:SPR1:SPR0
Table 83. SPI Master Baud Rate Selection
1.
2.
SPR2:SPR1:SPR0
The device is configured as a Master and the SSDIS control bit in SPCON is set.
This kind of configuration can be found when only one Master is driving the network
and there is no way that the SS pin will be pulled low. Therefore, the MODF flag in
the SPSTA will never be set
The Device is configured as a Slave with CPHA and SSDIS control bits set
kind of configuration can happen when the system comprises one Master and one
Slave only. Therefore, the device should always be selected and there is no reason
that the Master uses the SS pin to select the communicating Slave device.
Clearing SSDIS control bit does not clear MODF.
Special care should be taken not to set SSDIS control bit when CPHA = ’0’ because in
this mode, the SS is used to start the transmission.
000
001
010
100
101
011
110
111
Clock Rate
F
F
F
F
(1)
F
Reserved
F
Reserved
CK_SPI
CK_SPI
CK_SPI
CK_SPI
CK_SPI
CK_SPI
.
/128
/16
/32
/64
/ 8
/4
Baud Rate Divisor (BD)
N/A
128
N/A
16
32
64
4
8
4202F–SCR–07/2008
(2)
. This
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