AT89C5122D-RDTUM Atmel, AT89C5122D-RDTUM Datasheet - Page 107
![IC 8051 MCU FLASH 32K 64VQFP](/photos/6/81/68127/313-64-vqfp_sml.jpg)
AT89C5122D-RDTUM
Manufacturer Part Number
AT89C5122D-RDTUM
Description
IC 8051 MCU FLASH 32K 64VQFP
Manufacturer
Atmel
Series
89Cr
Datasheet
1.AT89C5122D-PSTUM.pdf
(208 pages)
Specifications of AT89C5122D-RDTUM
Core Processor
8051
Core Size
8-Bit
Speed
48MHz
Connectivity
SmartCard, SPI, UART/USART, USB
Peripherals
LED, POR, WDT
Number Of I /o
46
Program Memory Size
32KB (32K x 8)
Program Memory Type
FLASH
Ram Size
768 x 8
Voltage - Supply (vcc/vdd)
3 V ~ 5.5 V
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
64-TQFP, 64-VQFP
For Use With
AT89OCD-01 - USB EMULATOR FOR AT8XC51 MCUAT89STK-10 - KIT EVAL APPL MASS STORAGEAT89STK-03 - KIT STARTER FOR MCU AT8XC5122/23
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Data Converters
-
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Isochronous IN Transactions
in Standard Mode
Isochronous IN Transactions
in Ping-Pong Mode
4202F–SCR–07/2008
If the Host sends more bytes than supported by the endpoint FIFO, the overflow data
won’t be stored, but the USB controller will consider that the packet is valid if the CRC is
correct.
An endpoint should be first enabled and configured before being able to send Isochro-
nous packets.
The firmware should fill the FIFO with the data to be sent and set the TXRDY bit in the
UEPSTAX register to allow the USB controller to send the data stored in FIFO at the
next IN request concerning this endpoint.
If the TXRDY bit is not set when the IN request occurs, nothing will be sent by the USB
controller.
When the IN packet has been sent, the TXCMPL bit in the UEPSTAX register is set by
the USB controller. This triggers a USB interrupt if enabled. The firmware should clear
the TXCMPL bit before filling the endpoint FIFO with new data. The firmware should
never write more bytes than supported by the endpoint FIFO.
An endpoint should be first enabled and configured before being able to send Isochro-
nous packets.
The firmware should fill the FIFO bank 0 with the data to be sent and set the TXRDY bit
in the UEPSTAX register to allow the USB controller to send the data stored in FIFO at
the next IN request concerning the endpoint. The FIFO banks are automatically
switched, and the firmware can immediately write into the endpoint FIFO bank 1.
If the TXRDY bit is not set when the IN request occurs, nothing will be sent by the USB
controller.
When the IN packet concerning the bank 0 has been sent, the TXCMPL bit is set by the
USB controller. This triggers a USB interrupt if enabled. The firmware should clear the
TXCMPL bit before filling the endpoint FIFO bank 0 with new data. The FIFO banks are
then automatically switched.
When the IN packet concerning the bank 1 has been sent, the TXCMPL bit is set by the
USB controller. This triggers a USB interrupt if enabled. The firmware should clear the
TXCMPL bit before filling the endpoint FIFO bank 1 with new data.
The bank switch is performed by the USB controller each time the TXRDY bit is set by
the firmware. Until the TXRDY bit has been set by the firmware for an endpoint bank,
the USB controller won’t send anything at each IN requests concerning this bank.
The firmware should never write more bytes than supported by the endpoint FIFO.
AT83R5122, AT8xC5122/23
107
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