ATMEGA1280V-8CUR Atmel, ATMEGA1280V-8CUR Datasheet - Page 264
![MCU AVR 128K FLASH 8MHZ 100CBGA](/photos/6/89/68968/313-100-cbga_sml.jpg)
ATMEGA1280V-8CUR
Manufacturer Part Number
ATMEGA1280V-8CUR
Description
MCU AVR 128K FLASH 8MHZ 100CBGA
Manufacturer
Atmel
Series
AVR® ATmegar
Specifications of ATMEGA1280V-8CUR
Core Processor
AVR
Core Size
8-Bit
Speed
8MHz
Connectivity
EBI/EMI, I²C, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, POR, PWM, WDT
Number Of I /o
86
Program Memory Size
128KB (64K x 16)
Program Memory Type
FLASH
Eeprom Size
4K x 8
Ram Size
8K x 8
Voltage - Supply (vcc/vdd)
1.8 V ~ 5.5 V
Data Converters
A/D 16x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
100-TFBGA
Data Bus Width
8 bit
Data Ram Size
8 KB
Mounting Style
SMD/SMT
For Use With
ATSTK600-TQFP100 - STK600 SOCKET/ADAPTER 100-TQFPATSTK503 - STARTER KIT AVR EXP MODULE 100P
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
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Manufacturer
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23.7.5
Table 23-6.
23.7.6
2549M–AVR–09/10
Status Code
(TWSR)
Prescaler Bits
are 0
0xF8
0x00
Miscellaneous States
Combining Several TWI Modes
Status of the 2-wire Serial Bus
and 2-wire Serial Interface Hard-
ware
No relevant state information
available; TWINT = “0”
Bus error due to an illegal
START or STOP condition
Miscellaneous States
Figure 23-18. Formats and States in the Slave Transmitter Mode
There are two status codes that do not correspond to a defined TWI state, see
Status 0xF8 indicates that no relevant information is available because the TWINT Flag is not
set. This occurs between other states, and when the TWI is not involved in a serial transfer.
Status 0x00 indicates that a bus error has occurred during a 2-wire Serial Bus transfer. A bus
error occurs when a START or STOP condition occurs at an illegal position in the format frame.
Examples of such illegal positions are during the serial transfer of an address byte, a data byte,
or an acknowledge bit. When a bus error occurs, TWINT is set. To recover from a bus error, the
TWSTO Flag must set and TWINT must be cleared by writing a logic one to it. This causes the
TWI to enter the not addressed Slave mode and to clear the TWSTO Flag (no other bits in
TWCR are affected). The SDA and SCL lines are released, and no STOP condition is
transmitted.
In some cases, several TWI modes must be combined in order to complete the desired action.
Consider for example reading data from a serial EEPROM. Typically, such a transfer involves
the following steps:
1. The transfer must be initiated.
2. The EEPROM must be instructed what location should be read.
3. The reading must be performed.
4. The transfer must be finished.
Reception of the own
slave address and one or
more data bytes
Arbitration lost as master
and addressed as slave
Last data byte transmitted.
Switched to not addressed
slave (TWEA = '0')
To/from TWDR
No TWDR action
No TWDR action
From master to slave
From slave to master
S
Application Software Response
SLA
STA
0
ATmega640/1280/1281/2560/2561
No TWCR action
STO
R
1
DATA
To TWCR
$A8
$B0
TWINT
A
A
n
1
A
TWEA
X
DATA
Any number of data bytes
and their associated acknowledge bits
This number (contained in TWSR) corresponds
to a defined state of the Two-Wire Serial Bus. The
prescaler bits are zero or masked to zero
Next Action Taken by TWI Hardware
Wait or proceed current transfer
Only the internal hardware is affected, no STOP condi-
tion is sent on the bus. In all cases, the bus is released
and TWSTO is cleared.
$B8
A
DATA
$C0
$C8
A
A
Table
P or S
All 1's
23-6.
P or S
264
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