DSPIC30F5015-30I/PT Microchip Technology, DSPIC30F5015-30I/PT Datasheet - Page 157

• Manufacturer Part Number: DSPIC30F5015-30I/PT
• Description: IC DSPIC MCU/DSP 66K 64TQFP
• Manufacturer: Microchip Technology
• Series: dsPIC™ 30Fr

Specifications of DSPIC30F5015-30I/PT

• Program Memory Type: FLASH
• Program Memory Size: 66KB (22K x 24)
• Package / Case: 64-TFQFP
• Core Processor: dsPIC
• Core Size: 16-Bit
• Speed: 30 MIPs
• Connectivity: CAN, I²C, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, Motor Control PWM, QEI, POR, PWM, WDT
• Number Of I /o: 52
• Eeprom Size: 1K x 8
• Ram Size: 2K x 8
• Voltage - Supply (vcc/vdd): 2.5 V ~ 5.5 V
• Data Converters: A/D 16x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Product: DSCs
• Data Bus Width: 16 bit
• Processor Series: DSPIC30F
• Core: dsPIC
• Maximum Clock Frequency: 30 MHz
• Number Of Programmable I/os: 52
• Data Ram Size: 2 KB
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: 52713-733, 52714-737, 53276-922, EWDSPIC
• Development Tools By Supplier: PG164130, DV164035, DV244005, DV164005, PG164120, ICE4000, DM240002, DM330011
• Minimum Operating Temperature: - 40 C
• Package: 64TQFP
• Device Core: dsPIC
• Family Name: dsPIC30
• Maximum Speed: 30 MHz
• Operating Supply Voltage: 3.3|5 V
• Interface Type: CAN/I2C/SPI/UART
• On-chip Adc: 16-chx10-bit
• Number Of Timers: 5
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: XLT64PT5 - SOCKET TRAN ICE 64MQFP/TQFPAC164319 - MODULE SKT MPLAB PM3 64TQFPAC30F008 - MODULE SKT FOR DSPIC30F 64TQFPDV164005 - KIT ICD2 SIMPLE SUIT W/USB CABLE
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: DSPIC30F501530IPT

21.2.8
A write to the OSCCON register is intentionally made
difficult because it controls clock switching and clock
scaling.
To write to the OSCCON low byte, the following code
sequence must be executed without any other
instructions in between:
Byte write is allowed for one instruction cycle. Write the
desired value or use bit manipulation instruction.
To write to the OSCCON high byte, the following
instructions must be executed without any other
instructions in between:
Byte write is allowed for one instruction cycle. Write the
desired value or use bit manipulation instruction.
21.3
The
various kinds of Reset:
• Power-on Reset (POR)
• MCLR Reset during normal operation
• MCLR Reset during Sleep
• Watchdog Timer (WDT) Reset (during normal
• Programmable Brown-out Reset (BOR)
• RESET Instruction
• Reset cause by trap lockup (TRAPR)
• Reset caused by illegal opcode, or by using an
FIGURE 21-2:
© 2011 Microchip Technology Inc.
operation)
uninitialized W register as an Address Pointer
(IOPUWR)
Byte Write 0x46 to OSCCON low
Byte Write 0x57 to OSCCON low
Byte Write 0x46 to OSCCON low
Byte Write 0x57 to OSCCON low
MCLR
V
dsPIC30F5015/5016
DD
Reset
Instruction
RESET
PROTECTION AGAINST
ACCIDENTAL WRITES TO OSCCON
Illegal Opcode/
Uninitialized W Register
Trap Conflict
Brown-out
V
Sleep or Idle
Module
Detect
DD
WDT
Reset
RESET SYSTEM BLOCK DIAGRAM
Rise
BOREN
differentiates
Glitch Filter
Digital
POR
BOR
between
Different registers are affected in different ways by var-
ious Reset conditions. Most registers are not affected
by a WDT wake-up, since this is viewed as the resump-
tion of normal operation. Status bits from the RCON
register are set or cleared differently in different Reset
situations, as indicated in
used in software to determine the nature of the Reset.
A block diagram of the on-chip Reset circuit is shown in
Figure 21-2.
A MCLR noise filter is provided in the MCLR Reset
path. The filter detects and ignores small pulses.
Internally generated Resets do not drive MCLR pin low.
21.3.1
A power-on event will generate an internal POR pulse
when a V
at the POR circuit threshold voltage (V
nominally 1.85V. The device supply voltage character-
istics must meet specified starting voltage and rise rate
requirements. The POR pulse will reset a POR timer
and place the device in the Reset state. The POR also
selects the device clock source identified by the
oscillator configuration fuses.
The POR circuit inserts a small delay, T
nominally 10 μs and ensures that the device bias
circuits are stable. Furthermore, a user selected power-
up time-out (T
is based on Configuration bits and can be 0 ms (no
delay), 4 ms, 16 ms or 64 ms. The total delay is at
device power-up T
have expired, SYSRST will be negated on the next
leading edge of the Q1 clock, and the PC will jump to
the Reset vector.
The timing for the SYSRST signal is shown in
Figure 21-3 through Figure 21-5.
dsPIC30F5015/5016
DD
POR: POWER-ON RESET
rise is detected. The Reset pulse will occur
PWRT
POR
) is applied. The T
S
R
+ T
Table
PWRT
Q
. When these delays
21-5. These bits are
DS70149E-page 157
PWRT
POR
SYSRST
POR
), which is
parameter
, which is