AT89C51RE2-RLTUM Atmel, AT89C51RE2-RLTUM Datasheet - Page 155

• Manufacturer Part Number: AT89C51RE2-RLTUM
• Description: MCU 8051 128K FLASH 44-VQFP
• Manufacturer: Atmel
• Series: 89Cr

Specifications of AT89C51RE2-RLTUM

• Core Processor: 8051
• Core Size: 8-Bit
• Speed: 60MHz
• Connectivity: I²C, SPI, UART/USART
• Peripherals: POR, PWM, WDT
• Number Of I /o: 34
• Program Memory Size: 128KB (128K x 8)
• Program Memory Type: FLASH
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 5.5 V
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 44-TQFP, 44-VQFP
• Processor Series: AT89x
• Core: 8051
• Data Bus Width: 8 bit
• Data Ram Size: 8 KB
• Interface Type: UART, SPI
• Maximum Clock Frequency: 60 MHz
• Number Of Programmable I/os: 34
• Number Of Timers: 3
• Operating Supply Voltage: 2.7 V to 5.5 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: PK51, CA51, A51, ULINK2
• Development Tools By Supplier: AT89OCD-01
• Minimum Operating Temperature: - 40 C
• Height: 1.45 mm
• Length: 10.1 mm
• Supply Voltage (max): 5.5 V
• Supply Voltage (min): 2.7 V
• Width: 10.1 mm
• For Use With: AT89STK-11 - KIT STARTER FOR AT89C51RX2
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Data Converters: -
• Lead Free Status / Rohs Status: Details

Error Conditions
Mode Fault Error
(MODF)
7663E–8051–10/08
The following flags in the SPSCR register indicate the SPI error conditions:
Mode Fault error in Master mode SPI indicates that the level on the Slave Select (SS) pin is
inconsistent with the actual mode of the device.
•
MODF is set to warn that there may be a multi-master conflict for system control. In this case,
the SPI system is affected in the following ways:
Clearing the MODF bit is accomplished by a read of SPSCR register with MODF bit set, followed
by a write to the SPCON register. SPEN Control bit may be restored to its original set state after
the MODF bit has been cleared.
Figure 63. Mode Fault Conditions in Master Mode (Cpha =’1’/Cpol =’0’)
Note:
•
In slave mode, the MODF error is detected when SS goes high during a transmission.
A transmission begins when SS goes low and ends once the incoming SCK goes back to its idle
level following the shift of the eighteen data bit.
A MODF error occurs if a slave is selected (SS is low) and later unselected (SS is high) even if
no SCK is sent to that slave.
At any time, a’1’ on the SS pin of a slave SPI puts the MISO pin in a high impedance state and
internal state counter is cleared. Also, the slave SPI ignores all incoming SCK clocks, even if it
was already in the middle of a transmission. A new transmission will be performed as soon as
SS pin returns low.
Mode fault detection in Master mode:
–
–
–
Mode fault detection in Slave mode
When SS is discarded (SS disabled) it is not possible to detect a MODF error in master mode
because the SPI is internally unselected and the SS pin is a general purpose I/O.
An SPI receiver/error CPU interrupt request is generated
The SPEN bit in SPCON is cleared. This disables the SPI
The MSTR bit in SPCON is cleared
MOSI
SPI enable
SCK cycle #
SCK
(from master)
(from master)
MISO
(from slave)
SS
(master)
SS
(slave)
1
z
0
1
z
0
1
z
0
1
z
0
1
z
0
1
z
0
MODF detected
0
0
MSB
MSB
1
MODF detected
B6
B6
2
3
B5
AT89C51RE2
0
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