AT89C51RE2-RLTUM Atmel, AT89C51RE2-RLTUM Datasheet - Page 151

MCU 8051 128K FLASH 44-VQFP

AT89C51RE2-RLTUM

Manufacturer Part Number
AT89C51RE2-RLTUM
Description
MCU 8051 128K FLASH 44-VQFP
Manufacturer
Atmel
Series
89Cr
Datasheet

Specifications of AT89C51RE2-RLTUM

Core Processor
8051
Core Size
8-Bit
Speed
60MHz
Connectivity
I²C, SPI, UART/USART
Peripherals
POR, PWM, WDT
Number Of I /o
34
Program Memory Size
128KB (128K x 8)
Program Memory Type
FLASH
Ram Size
8K x 8
Voltage - Supply (vcc/vdd)
2.7 V ~ 5.5 V
Oscillator Type
External
Operating Temperature
-40°C ~ 85°C
Package / Case
44-TQFP, 44-VQFP
Processor Series
AT89x
Core
8051
Data Bus Width
8 bit
Data Ram Size
8 KB
Interface Type
UART, SPI
Maximum Clock Frequency
60 MHz
Number Of Programmable I/os
34
Number Of Timers
3
Operating Supply Voltage
2.7 V to 5.5 V
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
3rd Party Development Tools
PK51, CA51, A51, ULINK2
Development Tools By Supplier
AT89OCD-01
Minimum Operating Temperature
- 40 C
Height
1.45 mm
Length
10.1 mm
Supply Voltage (max)
5.5 V
Supply Voltage (min)
2.7 V
Width
10.1 mm
For Use With
AT89STK-11 - KIT STARTER FOR AT89C51RX2
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Data Converters
-
Lead Free Status / Rohs Status
 Details

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
AT89C51RE2-RLTUM
Manufacturer:
MSC
Quantity:
1 560
Part Number:
AT89C51RE2-RLTUM
Manufacturer:
Atmel
Quantity:
10 000
Functional
Description
Figure 57. SPI Module Block Diagram
Operating Modes
7663E–8051–10/08
SPSCR
SPCON
SPIF
SPR2
SPEN
-
Figure 57 shows a detailed structure of the SPI Module.
The Serial Peripheral Interface can be configured in one of the two modes: Master mode or
Slave mode. The configuration and initialization of the SPI Module is made through two
registers:
Once the SPI is configured, the data exchange is made using:
During an SPI transmission, data is simultaneously transmitted (shifted out serially) and
received (shifted in serially). A serial clock line (SCK) synchronizes shifting and sampling on the
two serial data lines (MOSI and MISO). A Slave Select line (SS) allows individual selection of a
Slave SPI device; Slave devices that are not selected do not interfere with SPI bus activities.
OVR
SSDIS
The Serial Peripheral Control register (SPCON)
The Serial Peripheral Status and Control Register (SPSCR)
The Serial Peripheral DATa register (SPDAT)
SPI
Control
MODF
MSTR
Internal Bus
SPTE
CPOL CPHA
UARTM SPTEIE MODFIE
SPR1
SPR0
SPDAT
Transmit Data Register
Receive Data Register
PERIPH
FCLK
7
Clock
Logic
Shift Register
6
5
4
3
SPI Interrupt
Request
2
1
0
AT89C51RE2
M
S
Pin
Control
Logic
8-bit bus
1-bit signal
MOSI
MISO
SCK
SS
151

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