AT32UC3B0256-A2UR Atmel, AT32UC3B0256-A2UR Datasheet - Page 385
AT32UC3B0256-A2UR
Manufacturer Part Number
AT32UC3B0256-A2UR
Description
MCU AVR32 256K FLASH 64-TQFP
Manufacturer
Atmel
Series
AVR®32 UC3r
Datasheet
1.AT32UC3B1512-Z1UT.pdf
(692 pages)
Specifications of AT32UC3B0256-A2UR
Package / Case
64-TQFP, 64-VQFP
Voltage - Supply (vcc/vdd)
1.65 V ~ 1.95 V
Operating Temperature
-40°C ~ 85°C
Speed
60MHz
Number Of I /o
44
Core Processor
AVR
Program Memory Type
FLASH
Ram Size
32K x 8
Program Memory Size
256KB (256K x 8)
Data Converters
A/D 8x10b
Oscillator Type
Internal
Peripherals
Brown-out Detect/Reset, DMA, POR, PWM, WDT
Connectivity
I²C, IrDA, SPI, SSC, UART/USART, USB
Core Size
32-Bit
Package
64TQFP
Device Core
AVR32
Family Name
AT32
Maximum Speed
60 MHz
Operating Supply Voltage
1.8|3.3 V
Data Bus Width
32 Bit
Number Of Programmable I/os
44
Interface Type
I2S/SPI/TWI/USART/USB
On-chip Adc
8-chx10-bit
Number Of Timers
3
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
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•Detailed description
TXINI
FIFOCON
Figure 22-18. Example of an IN Endpoint with 2 Data Banks
The data is written, following the next flow:
If the endpoint uses several banks, the current one can be written while the previous one is
being read by the host. Then, when the user clears FIFOCON, the following bank may already
be free and TXINI is set immediately.
An “Abort” stage can be produced when a zero-length OUT packet is received during an IN
stage of a control or isochronous IN transaction. The Kill IN Bank (KILLBK) bit in UECONn is
used to kill the last written bank. The best way to manage this abort is to apply the algorithm rep-
resented on
more details about the KILLBK bit.
• When the bank is empty, TXINI and FIFOCON are set, what triggers an EPnINT interrupt if
• The user acknowledges the interrupt by clearing TXINI.
• The user writes the data into the current bank by using the USB Pipe/Endpoint nFIFO Data
• The user allows the controller to send the bank and switches to the next bank (if any) by
TXINE is one.
virtual segment (see
481), until all the data frame is written or the bank is full (in which case RWALL is cleared and
the Byte Count (BYCT) field in UESTAn reaches the endpoint size).
clearing FIFOCON.
SW
write data to CPU
BANK 0
Figure 22-19 on page
SW
”USB Pipe/Endpoint n FIFO Data Register (USBFIFOnDATA)” on page
IN
SW
write data to CPU
386. See
BANK 1
(bank 0)
DATA
”Endpoint n Control Register” on page 442
SW
HW
ACK
SW
write data to CPU
IN
BANK0
AT32UC3B
(bank 1)
DATA
to have
ACK
385
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