AT32UC3B0256-A2UR Atmel, AT32UC3B0256-A2UR Datasheet - Page 402
AT32UC3B0256-A2UR
Manufacturer Part Number
AT32UC3B0256-A2UR
Description
MCU AVR32 256K FLASH 64-TQFP
Manufacturer
Atmel
Series
AVR®32 UC3r
Datasheet
1.AT32UC3B1512-Z1UT.pdf
(692 pages)
Specifications of AT32UC3B0256-A2UR
Package / Case
64-TQFP, 64-VQFP
Voltage - Supply (vcc/vdd)
1.65 V ~ 1.95 V
Operating Temperature
-40°C ~ 85°C
Speed
60MHz
Number Of I /o
44
Core Processor
AVR
Program Memory Type
FLASH
Ram Size
32K x 8
Program Memory Size
256KB (256K x 8)
Data Converters
A/D 8x10b
Oscillator Type
Internal
Peripherals
Brown-out Detect/Reset, DMA, POR, PWM, WDT
Connectivity
I²C, IrDA, SPI, SSC, UART/USART, USB
Core Size
32-Bit
Package
64TQFP
Device Core
AVR32
Family Name
AT32
Maximum Speed
60 MHz
Operating Supply Voltage
1.8|3.3 V
Data Bus Width
32 Bit
Number Of Programmable I/os
44
Interface Type
I2S/SPI/TWI/USART/USB
On-chip Adc
8-chx10-bit
Number Of Timers
3
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
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The UDDMAnSTATUS.CHEN bit is 0 and the UDDMAnSTATUS.LDNXTCHDESCEN is set indi-
cating that the DMA channel is pending until the endpoint is ready (received OUT packet).
As soon as an OUT packet is stored inside the endpoint, the UDDMAnSTATUS.CHACTIVE bit
is set to one. Then after a few cycle latency, the new descriptor is loaded from the memory and
the UDDMAnSTATUS.DESCLDSTA is set.
At the end of this DMA (for instance when the channel byte length has reached 0), the
UDDMAnCONTROL.CHEN bit is cleared, and then the UDDMAnSTATUS.CHEN bit is also
cleared. If the UDDMAnCONTROL.LDNXTCH value is one, a new descriptor is loaded.
This sequence is repeated until a last linked descriptor is processed. The last descriptor is
detected according to row 2 as shown in
At the end of the last descriptor, the UDDMAnCONTROL.CHEN bit is cleared. As a conse-
quence, after a few cycles latency, the UDDMAnSTATUS.CHEN bit is also cleared.
• Set up the chain of linked list of descripor in memory. Each descriptor is composed of 3 items
• Program the UDDMAnNEXTDESC register.
• Program the UDDMAnCONTROL according to Row 3 as shown in
: channel next descriptor address, channel destination address and channel control. The last
descriptor should be programmed according to row 2 as shown in
Figure 22-6 on page
449.
Figure 22-6 on page
Figure 22-6 on page
AT32UC3B
449.
449.
402
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