DSPIC33FJ256GP710A-E/PF Microchip Technology, DSPIC33FJ256GP710A-E/PF Datasheet - Page 258
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DSPIC33FJ256GP710A-E/PF
Manufacturer Part Number
DSPIC33FJ256GP710A-E/PF
Description
IC DSPIC DSC 256K FLASH 100TQFP
Manufacturer
Microchip Technology
Series
dsPIC™ 33Fr
Datasheets
1.DSPIC33FJ64GP206-IPT.pdf
(322 pages)
2.DSPIC33FJ64GP206A-IMR.pdf
(338 pages)
3.DSPIC33FJ128GP306A-IPT.pdf
(350 pages)
Specifications of DSPIC33FJ256GP710A-E/PF
Program Memory Type
FLASH
Program Memory Size
256KB (256K x 8)
Package / Case
100-TQFP
Core Processor
dsPIC
Core Size
16-Bit
Speed
40 MIPs
Connectivity
CAN, I²C, IrDA, LIN, SPI, UART/USART
Peripherals
AC'97, Brown-out Detect/Reset, DMA, I²S, POR, PWM, WDT
Number Of I /o
85
Ram Size
30K x 8
Voltage - Supply (vcc/vdd)
3 V ~ 3.6 V
Data Converters
A/D 32x10b/12b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 125°C
Product
DSCs
Data Bus Width
16 bit
Processor Series
DSPIC33F
Core
dsPIC
Maximum Clock Frequency
40 MHz
Number Of Programmable I/os
85
Data Ram Size
30 KB
Maximum Operating Temperature
+ 125 C
Mounting Style
SMD/SMT
3rd Party Development Tools
52713-733, 52714-737, 53276-922, EWDSPIC
Development Tools By Supplier
PG164130, DV164035, DV244005, DV164005, PG164120, DM240001, DM240002, DM330011, DM300019, DV164033, MA330011, MA330012, DM300024
Minimum Operating Temperature
- 40 C
Package
100TQFP
Device Core
dsPIC
Family Name
dSPIC33
Maximum Speed
40 MHz
Operating Supply Voltage
3.3 V
Interface Type
CAN/I2C/SPI/UART
On-chip Adc
64-chx10-bit|64-chx12-bit
Number Of Timers
9
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
DSPIC33FJ256GP710A-E/PF
Manufacturer:
Microchip Technology
Quantity:
135
Company:
Part Number:
DSPIC33FJ256GP710A-E/PF
Manufacturer:
Microchip Technology
Quantity:
10 000
- DSPIC33FJ64GP206-IPT PDF datasheet
- DSPIC33FJ64GP206A-IMR PDF datasheet #2
- DSPIC33FJ128GP306A-IPT PDF datasheet #3
- Current page: 258 of 350
- Download datasheet (6Mb)
Intellectual Property in collaborative system designs.
sections provide an overview of these features.
dsPIC33FJXXXGPX06A/X08A/X10A
22.5
dsPIC33FJXXXGPX06A/X08A/X10A devices imple-
ment a JTAG interface, which supports boundary scan
device testing, as well as in-circuit programming.
Detailed information on the interface will be provided in
future revisions of the document.
22.6
The dsPIC33F product families offer the advanced
implementation of CodeGuard™ Security. CodeGuard™
Security enables multiple parties to securely share
resources (memory, interrupts and peripherals) on a
single chip. This feature helps protect individual
When coupled with software encryption libraries,
CodeGuard Security can be used to securely update
Flash even when multiple IP are resident on the single
chip. The code protection features vary depending on
the actual dsPIC33F implemented. The following
The code protection features are controlled by the
Configuration registers: FBS, FSS and FGS.
22.7
dsPIC33FJXXXGPX06A/X08A/X10A family digital sig-
nal controllers can be serially programmed while in the
end application circuit. This is simply done with two
lines for clock and data and three other lines for power,
ground and the programming sequence. This allows
customers to manufacture boards with unprogrammed
devices and then program the digital signal controller
just before shipping the product. This also allows the
most recent firmware or a custom firmware, to be
programmed. Please refer to the “dsPIC33F/PIC24H
Flash
document for details about ICSP.
Any one out of three pairs of programming clock/data
pins may be used:
• PGEC1 and PGED1
• PGEC2 and PGED2
• PGEC3 and PGED3
DS70593C-page 258
Note:
JTAG Interface
Code Protection and
CodeGuard™ Security
Programming
In-Circuit Serial Programming
Refer to Section 23. “CodeGuard™
Security” (DS70199) in the “dsPIC33F/
PIC24H Family Reference Manual” for fur-
ther information on usage, configuration
and operation of CodeGuard™ Security.
Specification”
(DS70152)
22.8
When MPLAB
in-circuit debugging functionality is enabled. This
function allows simple debugging functions when used
with MPLAB IDE. Debugging functionality is controlled
through the PGECx (Emulation/Debug Clock) and
PGEDx (Emulation/Debug Data) pin functions.
Any one out of three pairs of debugging clock/data pins
may be used:
• PGEC1 and PGED1
• PGEC2 and PGED2
• PGEC3 and PGED3
To use the in-circuit debugger function of the device,
the design must implement ICSP connections to
MCLR, V
addition, when the feature is enabled, some of the
resources are not available for general use. These
resources include the first 80 bytes of data RAM and
two I/O pins.
In-Circuit Debugger
DD
, V
®
SS
ICD 2 is selected as a debugger, the
and the PGEDx/PGECx pin pair. In
© 2011 Microchip Technology Inc.
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