DSPIC33FJ256GP710A-E/PF Microchip Technology, DSPIC33FJ256GP710A-E/PF Datasheet - Page 191
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DSPIC33FJ256GP710A-E/PF
Manufacturer Part Number
DSPIC33FJ256GP710A-E/PF
Description
IC DSPIC DSC 256K FLASH 100TQFP
Manufacturer
Microchip Technology
Series
dsPIC™ 33Fr
Datasheets
1.DSPIC33FJ64GP206-IPT.pdf
(322 pages)
2.DSPIC33FJ64GP206A-IMR.pdf
(338 pages)
3.DSPIC33FJ128GP306A-IPT.pdf
(350 pages)
Specifications of DSPIC33FJ256GP710A-E/PF
Program Memory Type
FLASH
Program Memory Size
256KB (256K x 8)
Package / Case
100-TQFP
Core Processor
dsPIC
Core Size
16-Bit
Speed
40 MIPs
Connectivity
CAN, I²C, IrDA, LIN, SPI, UART/USART
Peripherals
AC'97, Brown-out Detect/Reset, DMA, I²S, POR, PWM, WDT
Number Of I /o
85
Ram Size
30K x 8
Voltage - Supply (vcc/vdd)
3 V ~ 3.6 V
Data Converters
A/D 32x10b/12b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 125°C
Product
DSCs
Data Bus Width
16 bit
Processor Series
DSPIC33F
Core
dsPIC
Maximum Clock Frequency
40 MHz
Number Of Programmable I/os
85
Data Ram Size
30 KB
Maximum Operating Temperature
+ 125 C
Mounting Style
SMD/SMT
3rd Party Development Tools
52713-733, 52714-737, 53276-922, EWDSPIC
Development Tools By Supplier
PG164130, DV164035, DV244005, DV164005, PG164120, DM240001, DM240002, DM330011, DM300019, DV164033, MA330011, MA330012, DM300024
Minimum Operating Temperature
- 40 C
Package
100TQFP
Device Core
dsPIC
Family Name
dSPIC33
Maximum Speed
40 MHz
Operating Supply Voltage
3.3 V
Interface Type
CAN/I2C/SPI/UART
On-chip Adc
64-chx10-bit|64-chx12-bit
Number Of Timers
9
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
DSPIC33FJ256GP710A-E/PF
Manufacturer:
Microchip Technology
Quantity:
135
Company:
Part Number:
DSPIC33FJ256GP710A-E/PF
Manufacturer:
Microchip Technology
Quantity:
10 000
- DSPIC33FJ64GP206-IPT PDF datasheet
- DSPIC33FJ64GP206A-IMR PDF datasheet #2
- DSPIC33FJ128GP306A-IPT PDF datasheet #3
- Current page: 191 of 350
- Download datasheet (6Mb)
REGISTER 17-1:
© 2011 Microchip Technology Inc.
bit 15
bit 7
Legend:
R = Readable bit
-n = Value at POR
bit 15
bit 14
bit 13
bit 12
bit 11
bit 10
bit 9
bit 8
bit 7
bit 6
I2CEN
R/W-0
R/W-0
GCEN
I2CEN: I2Cx Enable bit
1 = Enables the I2Cx module and configures the SDAx and SCLx pins as serial port pins
0 = Disables the I2Cx module. All I
Unimplemented: Read as ‘0’
I2CSIDL: Stop in Idle Mode bit
1 = Discontinue module operation when device enters an Idle mode
0 = Continue module operation in Idle mode
SCLREL: SCLx Release Control bit (when operating as I
1 = Release SCLx clock
0 = Hold SCLx clock low (clock stretch)
If STREN = 1:
Bit is R/W (i.e., software may write ‘0’ to initiate stretch and write ‘1’ to release clock). Hardware clear
at beginning of slave transmission. Hardware clear at end of slave reception.
If STREN = 0:
Bit is R/S (i.e., software may only write ‘1’ to release clock). Hardware clear at beginning of slave
transmission.
IPMIEN: Intelligent Peripheral Management Interface (IPMI) Enable bit
1 = IPMI mode is enabled; all addresses Acknowledged
0 = IPMI mode disabled
A10M: 10-bit Slave Address bit
1 = I2CxADD is a 10-bit slave address
0 = I2CxADD is a 7-bit slave address
DISSLW: Disable Slew Rate Control bit
1 = Slew rate control disabled
0 = Slew rate control enabled
SMEN: SMBus Input Levels bit
1 = Enable I/O pin thresholds compliant with SMBus specification
0 = Disable SMBus input thresholds
GCEN: General Call Enable bit (when operating as I
1 = Enable interrupt when a general call address is received in the I2CxRSR
0 = General call address disabled
STREN: SCLx Clock Stretch Enable bit (when operating as I
Used in conjunction with SCLREL bit.
1 = Enable software or receive clock stretching
0 = Disable software or receive clock stretching
STREN
R/W-0
(module is enabled for reception)
U-0
—
I2CxCON: I2Cx CONTROL REGISTER
dsPIC33FJXXXGPX06A/X08A/X10A
U = Unimplemented bit, read as ‘0’
W = Writable bit
‘1’ = Bit is set
I2CSIDL
ACKDT
R/W-0
R/W-0
R/W-1 HC
R/W-0 HC
SCLREL
ACKEN
2
C pins are controlled by port functions
HS = Set in hardware
‘0’ = Bit is cleared
R/W-0 HC
IPMIEN
R/W-0
RCEN
2
C slave)
2
C slave)
R/W-0 HC
2
R/W-0
A10M
C slave)
PEN
HC = Cleared in hardware
x = Bit is unknown
R/W-0 HC
DISSLW
R/W-0
RSEN
DS70593C-page 191
R/W-0 HC
SMEN
R/W-0
SEN
bit 8
bit 0
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