ATMEGA162V-8PU Atmel, ATMEGA162V-8PU Datasheet - Page 202

IC AVR MCU 16K 8MHZ 1.8V 40DIP

ATMEGA162V-8PU

Manufacturer Part Number
ATMEGA162V-8PU
Description
IC AVR MCU 16K 8MHZ 1.8V 40DIP
Manufacturer
Atmel
Series
AVR® ATmegar
Datasheets

Specifications of ATMEGA162V-8PU

Core Processor
AVR
Core Size
8-Bit
Speed
8MHz
Connectivity
EBI/EMI, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, POR, PWM, WDT
Number Of I /o
35
Program Memory Size
16KB (8K x 16)
Program Memory Type
FLASH
Eeprom Size
512 x 8
Ram Size
1K x 8
Voltage - Supply (vcc/vdd)
1.8 V ~ 5.5 V
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
40-DIP (0.600", 15.24mm)
Processor Series
ATMEGA16x
Core
AVR8
Data Bus Width
8 bit
Data Ram Size
1 KB
Interface Type
JTAG/SPI/USART
Maximum Clock Frequency
8 MHz
Number Of Programmable I/os
35
Number Of Timers
4
Operating Supply Voltage
1.8 V to 5.5 V
Maximum Operating Temperature
+ 85 C
Mounting Style
Through Hole
3rd Party Development Tools
EWAVR, EWAVR-BL
Minimum Operating Temperature
- 40 C
Package
40PDIP
Device Core
AVR
Family Name
ATmega
Maximum Speed
8 MHz
For Use With
ATSTK600-TQFP44 - STK600 SOCKET/ADAPTER 44-TQFPATSTK600 - DEV KIT FOR AVR/AVR32770-1007 - ISP 4PORT ATMEL AVR MCU SPI/JTAGATAVRISP2 - PROGRAMMER AVR IN SYSTEMATJTAGICE2 - AVR ON-CHIP D-BUG SYSTEMATSTK500 - PROGRAMMER AVR STARTER KIT
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Data Converters
-
Lead Free Status / Rohs Status
Lead free / RoHS Compliant

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
ATMEGA162V-8PU
Manufacturer:
IDT
Quantity:
74
On-chip debug
specific JTAG
instructions
PRIVATE0; 0x8
PRIVATE1; 0x9
PRIVATE2; 0xA
PRIVATE3; 0xB
On-chip Debug
Related Register in
I/O Memory
On-chip Debug
Register – OCDR
Using the JTAG
Programming
Capabilities
202
ATmega162/V
The On-chip debug support is considered being private JTAG instructions, and distributed within
ATMEL and to selected 3rd party vendors only. Instruction opcodes are listed for reference.
Private JTAG instruction for accessing On-chip debug system.
Private JTAG instruction for accessing On-chip debug system.
Private JTAG instruction for accessing On-chip debug system.
Private JTAG instruction for accessing On-chip debug system.
The OCDR Register provides a communication channel from the running program in the micro-
controller to the debugger. The CPU can transfer a byte to the debugger by writing to this
location. At the same time, an internal flag; I/O Debug Register Dirty – IDRD – is set to indicate
to the debugger that the register has been written. When the CPU reads the OCDR Register the
7 LSB will be from the OCDR Register, while the MSB is the IDRD bit. The debugger clears the
IDRD bit when it has read the information.
In some AVR devices, this register is shared with a standard I/O location. In this case, the OCDR
Register can only be accessed if the OCDEN Fuse is programmed, and the debugger enables
access to the OCDR Register. In all other cases, the standard I/O location is accessed.
Refer to the debugger documentation for further information on how to use this register.
Programming of AVR parts via JTAG is performed via the 4-pin JTAG port, TCK, TMS, TDI and
TDO. These are the only pins that need to be controlled/observed to perform JTAG program-
ming (in addition to power pins). It is not required to apply 12V externally. The JTAGEN Fuse
must be programmed and the JTD bit in the MCUSR Register must be cleared to enable the
JTAG Test Access Port.
The JTAG programming capability supports:
The Lock bit security is exactly as in parallel programming mode. If the Lock bits LB1 or LB2 are
programmed, the OCDEN Fuse cannot be programmed unless first doing a chip erase. This is a
security feature that ensures no backdoor exists for reading out the content of a secured device.
The details on programming through the JTAG interface and programming specific JTAG
instructions are given in the section
Bit
Read/Write
Initial Value
Flash programming and verifying.
EEPROM programming and verifying.
Fuse programming and verifying.
Lock bit programming and verifying.
MSB/IDRD
R/W
7
0
R/W
6
0
R/W
5
0
“Programming via the JTAG Interface” on page
R/W
4
0
R/W
3
0
R/W
2
0
R/W
1
0
LSB
R/W
0
0
OCDR
2513K–AVR–07/09
250.

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