PIC16LF767-I/SP Microchip Technology, PIC16LF767-I/SP Datasheet - Page 43
![IC PIC MCU FLASH 8KX14 28DIP](/photos/6/59/65908/150-28-dip_sml.jpg)
PIC16LF767-I/SP
Manufacturer Part Number
PIC16LF767-I/SP
Description
IC PIC MCU FLASH 8KX14 28DIP
Manufacturer
Microchip Technology
Series
PIC® 16Fr
Specifications of PIC16LF767-I/SP
Core Size
8-Bit
Program Memory Size
14KB (8K x 14)
Core Processor
PIC
Speed
10MHz
Connectivity
I²C, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, POR, PWM, WDT
Number Of I /o
25
Program Memory Type
FLASH
Ram Size
368 x 8
Voltage - Supply (vcc/vdd)
2 V ~ 5.5 V
Data Converters
A/D 11x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
28-DIP (0.300", 7.62mm)
Controller Family/series
PIC16LF
No. Of I/o's
25
Ram Memory Size
368Byte
Cpu Speed
20MHz
No. Of Timers
3
Processor Series
PIC16LF
Core
PIC
Data Bus Width
8 bit
Data Ram Size
368 B
Interface Type
AUSART, CCP, I2C, MSSP, SPI
Maximum Clock Frequency
20 MHz
Number Of Programmable I/os
25
Number Of Timers
8
Operating Supply Voltage
2 V to 5.5 V
Maximum Operating Temperature
+ 85 C
Mounting Style
Through Hole
3rd Party Development Tools
52715-96, 52716-328, 52717-734
Development Tools By Supplier
PG164130, DV164035, DV244005, DV164005, PG164120, ICE2000
Minimum Operating Temperature
- 40 C
On-chip Adc
10 bit
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Lead Free Status / Rohs Status
Details
- Current page: 43 of 276
- Download datasheet (6Mb)
4.7
4.7.1
When SCS bits are configured to run from the INTRC,
a clock transition is generated if the system clock is not
already using the INTRC. The event will clear the
OSTS bit and switch the system clock from the primary
system clock (if SCS<1:0> = 00) determined by the
value contained in the configuration bits, or from the
T1OSC (if SCS<1:0> = 01) to the INTRC clock option
and shut-down the primary system clock to conserve
power. Clock switching will not occur if the primary
system clock is already configured as INTRC.
FIGURE 4-7:
2004 Microchip Technology Inc.
SCS<1:0>
Note 1:
Program
INTOSC
Counter
System
OSC1
Clock
2:
3:
4:
Power-Managed Modes
T
T
T
T
INP
OSC
SCS
DLY
Q1
RC_RUN MODE
T
= 32 s typical.
OSC (2)
= 8 T
= 1 T
Q2
= 50 ns minimum.
PC
Q3
INP
INP
.
.
Q4
TIMING DIAGRAM FOR XT, HS, LP, EC, EXTRC TO RC_RUN MODE
T
Q1
DLY (4)
T
INP
(1)
T
SCS
(3)
PC + 1
If the system clock does not come from the INTRC
(31.25 kHz) when the SCS bits are changed and the
IRCF bits in the OSCCON register are configured for a
frequency other than INTRC, the frequency may not be
stable immediately. The IOFS bit (OSCCON<2>) will
be set when the INTOSC or postscaler frequency is
stable, after 4 ms (approx.).
After a clock switch has been executed, the OSTS bit
is cleared, indicating a low-power mode and the device
does not run from the primary system clock. The inter-
nal Q clocks are held in the Q1 state until eight falling
edge clocks are counted on the INTRC oscillator. After
the eight clock periods have transpired, the clock input
to the Q clocks is released and operation resumes (see
Figure 4-7).
Q1
Q2
Q3
Q4
PIC16F7X7
Q1
Q2
PC + 2
DS30498C-page 41
Q3
Q4
PC + 3
Q1
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