PIC16LF767-I/SP Microchip Technology, PIC16LF767-I/SP Datasheet - Page 192
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PIC16LF767-I/SP
Manufacturer Part Number
PIC16LF767-I/SP
Description
IC PIC MCU FLASH 8KX14 28DIP
Manufacturer
Microchip Technology
Series
PIC® 16Fr
Specifications of PIC16LF767-I/SP
Core Size
8-Bit
Program Memory Size
14KB (8K x 14)
Core Processor
PIC
Speed
10MHz
Connectivity
I²C, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, POR, PWM, WDT
Number Of I /o
25
Program Memory Type
FLASH
Ram Size
368 x 8
Voltage - Supply (vcc/vdd)
2 V ~ 5.5 V
Data Converters
A/D 11x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
28-DIP (0.300", 7.62mm)
Controller Family/series
PIC16LF
No. Of I/o's
25
Ram Memory Size
368Byte
Cpu Speed
20MHz
No. Of Timers
3
Processor Series
PIC16LF
Core
PIC
Data Bus Width
8 bit
Data Ram Size
368 B
Interface Type
AUSART, CCP, I2C, MSSP, SPI
Maximum Clock Frequency
20 MHz
Number Of Programmable I/os
25
Number Of Timers
8
Operating Supply Voltage
2 V to 5.5 V
Maximum Operating Temperature
+ 85 C
Mounting Style
Through Hole
3rd Party Development Tools
52715-96, 52716-328, 52717-734
Development Tools By Supplier
PG164130, DV164035, DV244005, DV164005, PG164120, ICE2000
Minimum Operating Temperature
- 40 C
On-chip Adc
10 bit
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Lead Free Status / Rohs Status
Details
- Current page: 192 of 276
- Download datasheet (6Mb)
PIC16F7X7
15.17.4.2
When a clock failure is detected, SCS<1:0> will be
forced to ‘10’ which will reset the WDT (if enabled).
15.17.4.3
The FSCM is designed to detect oscillator failure at any
point after the device has exited Power-on Reset
(POR) or low-power Sleep mode. When the primary
system clock is EC, RC or INTRC modes, monitoring
can begin immediately following these events.
For oscillator modes involving a crystal or resonator
(HS, LP or XT), the situation is somewhat different.
Since the oscillator may require a start-up time consid-
erably longer than the FSCM sample clock time, a false
clock failure may be detected. To prevent this, the
internal oscillator block is automatically configured as
the system clock and functions until the primary clock
is stable (the OST and PLL timers have timed out). This
is identical to Two-Speed Start-up mode. Once the
primary clock is stable, the INTRC returns to its role as
the FSCM source.
15.18 Power-Down Mode (Sleep)
Power-Down mode is entered by executing a SLEEP
instruction.
If enabled, the Watchdog Timer will be cleared but
keeps running, the PD bit (Status<3>) is cleared, the
TO (Status<4>) bit is set and the oscillator driver is
turned off. The I/O ports maintain the status they had
before the SLEEP instruction was executed (driving
high, low or high-impedance).
For lowest current consumption in this mode, place all
I/O pins at either V
is drawing current from the I/O pin, power-down the A/D
and disable external clocks. Pull all I/O pins that are
high-impedance inputs, high or low externally, to avoid
switching currents caused by floating inputs. The T0CKI
input should also be at V
consumption. The contribution from on-chip pull-ups on
PORTB should also be considered.
The MCLR pin must be at a logic high level (V
DS30498C-page 190
Note:
The same logic that prevents false
oscillator failure interrupts on POR, or
wake from Sleep, will also prevent the
detection of the oscillator’s failure to start
at all following these events. This can be
avoided by monitoring the OSTS bit and
using a timing routine to determine if the
oscillator is taking too long to start. Even
so, no oscillator failure interrupt will be
flagged.
FSCM and the Watchdog Timer
POR or Wake from Sleep
DD
or V
SS
DD
, ensure no external circuitry
or V
SS
for lowest current
IHMC
).
15.18.1
The device can wake-up from Sleep through one of the
following events:
1.
2.
3.
External MCLR Reset will cause a device Reset. All
other events are considered a continuation of program
execution and cause a “wake-up”. The TO and PD bits
in the Status register can be used to determine the
cause of the device Reset. The PD bit, which is set on
power-up, is cleared when Sleep is invoked. The TO bit
is cleared if a WDT time-out occurred and caused
wake-up.
The following peripheral interrupts can wake the device
from Sleep:
1.
2.
3.
4.
5.
6.
7.
8.
9.
Other peripherals cannot generate interrupts, since
during Sleep, no on-chip clocks are present.
When the SLEEP instruction is being executed, the next
instruction (PC + 1) is prefetched. For the device to
wake-up through an interrupt event, the corresponding
interrupt enable bit must be set (enabled). Wake-up
occurs regardless of the state of the GIE bit. If the GIE
bit is clear (disabled), the device continues execution at
the instruction after the SLEEP instruction. If the GIE bit
is set (enabled), the device executes the instruction
after the SLEEP instruction and then branches to the
interrupt address (0004h). In cases where the execu-
tion of the instruction following SLEEP is not desirable,
the user should have a NOP after the SLEEP instruction.
External Reset input on MCLR pin.
Watchdog
enabled).
Interrupt from INT pin, RB port change or a
peripheral interrupt.
TMR1 interrupt. Timer1 must be operating as an
asynchronous counter.
CCP Capture mode interrupt.
Special event trigger (Timer1 in Asynchronous
mode using an external clock).
SSP (Start/Stop) bit detect interrupt.
SSP transmit or receive in Slave mode (SPI/I
A/D conversion (when A/D clock source is RC).
EEPROM write operation completion.
Comparator output changes state.
AUSART RX or TX (Synchronous Slave mode).
WAKE-UP FROM SLEEP
Timer
2004 Microchip Technology Inc.
wake-up
(if
WDT
was
2
C).
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