ATMEGA6450A-AU Atmel, ATMEGA6450A-AU Datasheet - Page 25
![IC MCU AVR 64K FLASH 100TQFP](/photos/6/70/67048/313-100-tqfp_sml.jpg)
ATMEGA6450A-AU
Manufacturer Part Number
ATMEGA6450A-AU
Description
IC MCU AVR 64K FLASH 100TQFP
Manufacturer
Atmel
Series
AVR® ATmegar
Specifications of ATMEGA6450A-AU
Core Processor
AVR
Core Size
8-Bit
Speed
20MHz
Connectivity
SPI, UART/USART, USI
Peripherals
Brown-out Detect/Reset, POR, PWM, WDT
Number Of I /o
69
Program Memory Size
64KB (32K x 16)
Program Memory Type
FLASH
Eeprom Size
2K x 8
Ram Size
4K x 8
Voltage - Supply (vcc/vdd)
1.8 V ~ 5.5 V
Data Converters
A/D 8x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
100-TFQFP
Processor Series
ATmega
Core
AVR
Data Bus Width
8 bit
Data Ram Size
4 KB
Interface Type
SPI, USART
Maximum Clock Frequency
20 MHz
Number Of Programmable I/os
69
Number Of Timers
3
Operating Supply Voltage
3.3 V
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
Minimum Operating Temperature
- 40 C
Operating Temperature Range
- 40 C to + 85 C
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
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Manufacturer
Quantity
Price
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- Download datasheet (37Mb)
7.4
7.5
8285B–AVR–03/11
I/O Memory
General Purpose I/O Registers
ATmega165A/165PA/325A/325PA/3250A/3250PA/6
be used. If a reset occurs while a write operation is in progress, the write operation will be com-
pleted provided that the power supply voltage is sufficient.
The I/O space definition is shown in
All ATmega165A/165PA/325A/325PA/3250A/3250PA/645A/645P/6450A/6450P I/Os and
peripherals are placed in the I/O space. All I/O locations may be accessed by the LD/LDS/LDD
and ST/STS/STD instructions, transferring data between the 32 general purpose working regis-
ters and the I/O space. I/O Registers within the address range 0x00 - 0x1F are directly bit-
accessible using the SBI and CBI instructions. In these registers, the value of single bits can be
checked by using the SBIS and SBIC instructions. Refer to the instruction set section for more
details. When using the I/O specific commands IN and OUT, the I/O addresses 0x00 - 0x3F
must be used. When addressing I/O Registers as data space using LD and ST instructions,
0x20 must be added to these addresses.
The ATmega165A/165PA/325A/325PA/3250A/3250PA/645A/645P/6450A/6450P is a complex
microcontroller with more peripheral units than can be supported within the 64 location reserved
in Opcode for the IN and OUT instructions. For the Extended I/O space from 0x60 - 0xFF in
SRAM, only the ST/STS/STD and LD/LDS/LDD instructions can be used.
For compatibility with future devices, reserved bits should be written to zero if accessed.
Reserved I/O memory addresses should never be written.
Some of the Status Flags are cleared by writing a logical one to them. Note that, unlike most
other AVRs, the CBI and SBI instructions will only operate on the specified bit, and can therefore
be used on registers containing such Status Flags. The CBI and SBI instructions work with reg-
isters 0x00 to 0x1F only.
The I/O and peripherals control registers are explained in later sections.
The ATmega165A/165PA/325A/325PA/3250A/3250PA/645A/645P/6450A/6450P contains
three General Purpose I/O Registers. These registers can be used for storing any information,
and they are particularly useful for storing global variables and Status Flags. General Purpose
I/O Registers within the address range 0x00 - 0x1F are directly bit-accessible using the SBI,
CBI, SBIS, and SBIC instructions.
”Register Summary” on page
649.
25
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