ATMEGA6450A-AU Atmel, ATMEGA6450A-AU Datasheet - Page 145
![IC MCU AVR 64K FLASH 100TQFP](/photos/6/70/67048/313-100-tqfp_sml.jpg)
ATMEGA6450A-AU
Manufacturer Part Number
ATMEGA6450A-AU
Description
IC MCU AVR 64K FLASH 100TQFP
Manufacturer
Atmel
Series
AVR® ATmegar
Specifications of ATMEGA6450A-AU
Core Processor
AVR
Core Size
8-Bit
Speed
20MHz
Connectivity
SPI, UART/USART, USI
Peripherals
Brown-out Detect/Reset, POR, PWM, WDT
Number Of I /o
69
Program Memory Size
64KB (32K x 16)
Program Memory Type
FLASH
Eeprom Size
2K x 8
Ram Size
4K x 8
Voltage - Supply (vcc/vdd)
1.8 V ~ 5.5 V
Data Converters
A/D 8x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
100-TFQFP
Processor Series
ATmega
Core
AVR
Data Bus Width
8 bit
Data Ram Size
4 KB
Interface Type
SPI, USART
Maximum Clock Frequency
20 MHz
Number Of Programmable I/os
69
Number Of Timers
3
Operating Supply Voltage
3.3 V
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
Minimum Operating Temperature
- 40 C
Operating Temperature Range
- 40 C to + 85 C
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
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Manufacturer
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17.7
17.7.1
17.7.2
8285B–AVR–03/11
Modes of Operation
Normal Mode
Clear Timer on Compare Match (CTC) Mode
ATmega165A/165PA/325A/325PA/3250A/3250PA/6
on the OC2A Register is to be performed on the next compare match. For compare output
actions in the non-PWM modes refer to
Table 17-4 on page
A change of the COM2A[1:0] bits state will have effect at the first compare match after the bits
are written. For non-PWM modes, the action can be forced to have immediate effect by using
the FOC2A strobe bits.
The mode of operation, i.e., the behavior of the Timer/Counter and the Output Compare pins, is
defined by the combination of the Waveform Generation mode (WGM2[1:0]) and Compare Out-
put mode (COM2A[1:0]) bits. The Compare Output mode bits do not affect the counting
sequence, while the Waveform Generation mode bits do. The COM2A[1:0] bits control whether
the PWM output generated should be inverted or not (inverted or non-inverted PWM). For non-
PWM modes the COM2A[1:0] bits control whether the output should be set, cleared, or toggled
at a compare match
For detailed timing information refer to
The simplest mode of operation is the Normal mode (WGM2[1:0] = 0). In this mode the counting
direction is always up (incrementing), and no counter clear is performed. The counter simply
overruns when it passes its maximum 8-bit value (TOP = 0xFF) and then restarts from the bot-
tom (0x00). In normal operation the Timer/Counter Overflow Flag (TOV2) will be set in the same
timer clock cycle as the TCNT2 becomes zero. The TOV2 Flag in this case behaves like a ninth
bit, except that it is only set, not cleared. However, combined with the timer overflow interrupt
that automatically clears the TOV2 Flag, the timer resolution can be increased by software.
There are no special cases to consider in the Normal mode, a new counter value can be written
anytime.
The Output Compare unit can be used to generate interrupts at some given time. Using the Out-
put Compare to generate waveforms in Normal mode is not recommended, since this will
occupy too much of the CPU time.
In Clear Timer on Compare or CTC mode (WGM[1:0] = 2), the OCR2A Register is used to
manipulate the counter resolution. In CTC mode the counter is cleared to zero when the counter
value (TCNT2) matches the OCR2A. The OCR2A defines the top value for the counter, hence
also its resolution. This mode allows greater control of the compare match output frequency. It
also simplifies the operation of counting external events.
The timing diagram for the CTC mode is shown in
increases until a compare match occurs between TCNT2 and OCR2A, and then counter
(TCNT2) is cleared.
155, and for phase correct PWM refer to
(See ”Compare Match Output Unit” on page
”Timer/Counter Timing Diagrams” on page
Table 17-3 on page
Figure
17-5. The counter value (TCNT2)
Table 17-5 on page
155. For fast PWM mode, refer to
144.).
155.
149.
145
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