ATMEGA6450A-AU Atmel, ATMEGA6450A-AU Datasheet - Page 219
ATMEGA6450A-AU
Manufacturer Part Number
ATMEGA6450A-AU
Description
IC MCU AVR 64K FLASH 100TQFP
Manufacturer
Atmel
Series
AVR® ATmegar
Specifications of ATMEGA6450A-AU
Core Processor
AVR
Core Size
8-Bit
Speed
20MHz
Connectivity
SPI, UART/USART, USI
Peripherals
Brown-out Detect/Reset, POR, PWM, WDT
Number Of I /o
69
Program Memory Size
64KB (32K x 16)
Program Memory Type
FLASH
Eeprom Size
2K x 8
Ram Size
4K x 8
Voltage - Supply (vcc/vdd)
1.8 V ~ 5.5 V
Data Converters
A/D 8x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
100-TFQFP
Processor Series
ATmega
Core
AVR
Data Bus Width
8 bit
Data Ram Size
4 KB
Interface Type
SPI, USART
Maximum Clock Frequency
20 MHz
Number Of Programmable I/os
69
Number Of Timers
3
Operating Supply Voltage
3.3 V
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
Minimum Operating Temperature
- 40 C
Operating Temperature Range
- 40 C to + 85 C
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
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22.6
8285B–AVR–03/11
Changing Channel or Reference Selection
ATmega165A/165PA/325A/325PA/3250A/3250PA/6
Figure 22-7. ADC Timing Diagram, Free Running Conversion
Table 22-1.
The MUXn and REFS1:0 bits in the ADMUX Register are single buffered through a temporary
register to which the CPU has random access. This ensures that the channels and reference
selection only takes place at a safe point during the conversion. The channel and reference
selection is continuously updated until a conversion is started. Once the conversion starts, the
channel and reference selection is locked to ensure a sufficient sampling time for the ADC. Con-
tinuous updating resumes in the last ADC clock cycle before the conversion completes (ADIF in
ADCSRA is set). Note that the conversion starts on the following rising ADC clock edge after
ADSC is written. The user is thus advised not to write new channel or reference selection values
to ADMUX until one ADC clock cycle after ADSC is written.
If Auto Triggering is used, the exact time of the triggering event can be indeterministic. Special
care must be taken when updating the ADMUX Register, in order to control which conversion
will be affected by the new settings.
If both ADATE and ADEN is written to one, an interrupt event can occur at any time. If the
ADMUX Register is changed in this period, the user cannot tell if the next conversion is based
on the old or the new settings. ADMUX can be safely updated in the following ways:
When updating ADMUX in one of these conditions, the new settings will affect the next ADC
conversion.
Condition
First conversion
Normal conversions, single ended
Auto Triggered conversions
a. When ADATE or ADEN is cleared.
b. During conversion, minimum one ADC clock cycle after the trigger event.
c. After a conversion, before the Interrupt Flag used as trigger source is cleared.
ADC Conversion Time
Cycle Number
ADC Clock
ADSC
ADIF
ADCH
ADCL
Conversion
Complete
One Conversion
11
Sample & Hold (Cycles from
Start of Conversion)
12
13
Next Conversion
1
13.5
1.5
Sign and MSB of Result
LSB of Result
2
2
MUX and REFS
Update
3
Sample & Hold
4
Conversion Time (Cycles)
13.5
25
13
219
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