PIC18LF4423-I/PT Microchip Technology, PIC18LF4423-I/PT Datasheet - Page 37
![IC PIC MCU FLASH 8KX16 44TQFP](/photos/6/82/68251/c04-076_pt_sml.jpg)
PIC18LF4423-I/PT
Manufacturer Part Number
PIC18LF4423-I/PT
Description
IC PIC MCU FLASH 8KX16 44TQFP
Manufacturer
Microchip Technology
Series
PIC® 18Fr
Datasheets
1.PIC18F2423-ISP.pdf
(54 pages)
2.PIC18F2423-ISP.pdf
(8 pages)
3.PIC18F2423-ISP.pdf
(34 pages)
4.PIC18F2523-ISO.pdf
(392 pages)
Specifications of PIC18LF4423-I/PT
Core Size
8-Bit
Program Memory Size
16KB (8K x 16)
Core Processor
PIC
Speed
40MHz
Connectivity
I²C, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, HLVD, POR, PWM, WDT
Number Of I /o
36
Program Memory Type
FLASH
Eeprom Size
256 x 8
Ram Size
768 x 8
Voltage - Supply (vcc/vdd)
2 V ~ 5.5 V
Data Converters
A/D 13x12b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
44-TQFP, 44-VQFP
Controller Family/series
PIC18
No. Of I/o's
36
Eeprom Memory Size
256Byte
Ram Memory Size
768Byte
Cpu Speed
40MHz
No. Of Timers
4
Processor Series
PIC18LF
Core
PIC
Data Bus Width
8 bit
Data Ram Size
768 B
Interface Type
EUSART, I2C, MSSP, SPI
Maximum Clock Frequency
40 MHz
Number Of Programmable I/os
36
Number Of Timers
4
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
3rd Party Development Tools
52715-96, 52716-328, 52717-734, 52712-325, EWPIC18
Development Tools By Supplier
PG164130, DV164035, DV244005, DV164005, PG164120, ICE2000, DM163022, DV164136
Minimum Operating Temperature
- 40 C
On-chip Adc
12 bit, 13 Channel
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Lead Free Status / RoHS Status
Lead free / RoHS Compliant, Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
PIC18LF4423-I/PT
Manufacturer:
Microchip Technology
Quantity:
10 000
- PIC18F2423-ISP PDF datasheet
- PIC18F2423-ISP PDF datasheet #2
- PIC18F2423-ISP PDF datasheet #3
- PIC18F2523-ISO PDF datasheet #4
- Current page: 37 of 392
- Download datasheet (7Mb)
FIGURE 3-1:
FIGURE 3-2:
3.2.3
In RC_RUN mode, the CPU and peripherals are
clocked from the internal oscillator block using the
INTOSC multiplexer. In this mode, the primary clock is
shut down. When using the INTRC source, this mode
provides the best power conservation of all the Run
modes, while still executing code. It works well for user
applications which are not highly timing sensitive or do
not require high-speed clocks at all times.
If the primary clock source is the internal oscillator
block (either INTRC or INTOSC), there are no distin-
guishable
RC_RUN modes during execution. However, a clock
switch delay will occur during entry to and exit from
RC_RUN mode. Therefore, if the primary clock source
is the internal oscillator block, the use of RC_RUN
mode is not recommended.
© 2007 Microchip Technology Inc.
Peripheral
Note 1: Clock transition typically occurs within 2-4 T
Program
Counter
T1OSI
OSC1
Note1: T
Clock
Clock
RC_RUN MODE
CPU Clock
CPU
PLL Clock
Peripheral
differences
Program
Counter
Output
2: Clock transition typically occurs within 2-4 T
T1OSI
OSC1
Clock
Q1
OST
SCS1:SCS0 bits Changed
Q2
= 1024 T
TRANSITION TIMING FOR ENTRY TO SEC_RUN MODE
TRANSITION TIMING FROM SEC_RUN MODE TO PRI_RUN MODE (HSPLL)
PC
Q3
between
Q4
OSC
; T
Q1
PLL
Q1
T
1
= 2 ms (approx). These intervals are not shown to scale.
OST
PRI_RUN
(1)
PC
2
Q2
Clock Transition
PIC18F2423/2523/4423/4523
3
OSC
T
OSTS bit Set
Q3
PLL (1)
and
Preliminary
.
OSC
.
(1)
PC + 2
n-1
Q4
This mode is entered by setting the SCS1 bit to ‘1’.
Although it is ignored, it is recommended that the SCS0
bit also be cleared; this is to maintain software compat-
ibility with future devices. When the clock source is
switched to the INTOSC multiplexer (see Figure 3-3),
the primary oscillator is shut down and the OSTS bit is
cleared. The IRCF bits may be modified at any time to
immediately change the clock speed.
n
Q1
1
Note:
Transition
2
Clock
n-1 n
(2)
Q2
Caution should be used when modifying a
single IRCF bit. If V
possible to select a higher clock speed
than is supported by the low V
Improper device operation may result if
the V
(see Figure 26-1 and Figure 26-2).
PC + 2
Q3
DD
/F
Q2
OSC
Q4
Q3 Q4
specifications are violated
Q1
DD
Q1
PC + 4
Q2
is less than 3V, it is
PC + 4
Q2
DS39755B-page 35
Q3
Q3
DD
.
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