PIC18LF4423-I/PT Microchip Technology, PIC18LF4423-I/PT Datasheet - Page 269

• Manufacturer Part Number: PIC18LF4423-I/PT
• Description: IC PIC MCU FLASH 8KX16 44TQFP
• Manufacturer: Microchip Technology
• Series: PIC® 18Fr

Specifications of PIC18LF4423-I/PT

• Core Size: 8-Bit
• Program Memory Size: 16KB (8K x 16)
• Core Processor: PIC
• Speed: 40MHz
• Connectivity: I²C, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, HLVD, POR, PWM, WDT
• Number Of I /o: 36
• Program Memory Type: FLASH
• Eeprom Size: 256 x 8
• Ram Size: 768 x 8
• Voltage - Supply (vcc/vdd): 2 V ~ 5.5 V
• Data Converters: A/D 13x12b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 44-TQFP, 44-VQFP
• Controller Family/series: PIC18
• No. Of I/o's: 36
• Eeprom Memory Size: 256Byte
• Ram Memory Size: 768Byte
• Cpu Speed: 40MHz
• No. Of Timers: 4
• Processor Series: PIC18LF
• Core: PIC
• Data Bus Width: 8 bit
• Data Ram Size: 768 B
• Interface Type: EUSART, I2C, MSSP, SPI
• Maximum Clock Frequency: 40 MHz
• Number Of Programmable I/os: 36
• Number Of Timers: 4
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: 52715-96, 52716-328, 52717-734, 52712-325, EWPIC18
• Development Tools By Supplier: PG164130, DV164035, DV244005, DV164005, PG164120, ICE2000, DM163022, DV164136
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 12 bit, 13 Channel
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant

23.5
The overall structure of the code protection on the
PIC18 Flash devices differs significantly from other
PIC
The user program memory is divided into five blocks.
One of these is a boot block of 2 Kbytes. The remainder
of the memory is divided into four blocks on binary
boundaries.
FIGURE 23-5:
TABLE 23-3:
© 2007 Microchip Technology Inc.
300008h
300009h
30000Ah
30000Bh
30000Ch
30000Dh
Legend: Shaded cells are unimplemented.
Note 1:
®
MCU devices.
File Name
Program Verification and
Code Protection
Unimplemented in PIC18LF2423/4423 devices; maintain this bit set.
(PIC18LF2423/4423)
CONFIG5L
CONFIG5H
CONFIG6L
CONFIG6H
CONFIG7L
CONFIG7H
Unimplemented
Boot Block
16 Kbytes
SUMMARY OF CODE PROTECTION REGISTERS
Read ‘0’s
Block 0
Block 1
MEMORY SIZE/DEVICE
CODE-PROTECTED PROGRAM MEMORY FOR PIC18LF2423/2523/4423/4523
WRTD
Bit 7
CPD
—
—
—
—
(PIC18LF2523/4523)
EBTRB
WRTB
Bit 6
CPB
Unimplemented
—
—
—
Boot Block
32 Kbytes
Read ‘0’s
Block 0
Block 1
Block 2
Block 3
PIC18F2423/2523/4423/4523
WRTC
Bit 5
Preliminary
—
—
—
—
—
000000h
0007FFh
000800h
001FFFh
002000h
003FFFh
004000h
005FFFh
006000h
007FFFh
1FFFFFh
Address
Bit 4
Range
—
—
—
—
—
—
Each of the five blocks has three code protection bits
associated with them. They are:
• Code-Protect bit (CPn)
• Write-Protect bit (WRTn)
• External Block Table Read bit (EBTRn)
Figure 23-5 shows the program memory organization
for 16 and 32-Kbyte devices and the specific code pro-
tection bit associated with each block. The actual
locations of the bits are summarized in Table 23-3.
EBTR3
WRT3
CP3
Bit 3
—
—
—
(Unimplemented Memory Space)
(1)
(1)
(1)
Block Code Protection
CPB, WRTB, EBTRB
CP0, WRT0, EBTR0
CP1, WRT1, EBTR1
CP2, WRT2, EBTR2
CP3, WRT3, EBTR3
EBTR2
Controlled By:
WRT2
CP2
Bit 2
—
—
—
(1)
(1)
(1)
EBTR1
WRT1
Bit 1
CP1
DS39755B-page 267
—
—
—
EBTR0
WRT0
Bit 0
CP0
—
—
—