PIC16F876A-I/SO Microchip Technology, PIC16F876A-I/SO Datasheet - Page 347
![IC MCU FLASH 8KX14 EE 28SOIC](/photos/6/59/65909/150-28-soic_sml.jpg)
PIC16F876A-I/SO
Manufacturer Part Number
PIC16F876A-I/SO
Description
IC MCU FLASH 8KX14 EE 28SOIC
Manufacturer
Microchip Technology
Series
PIC® 16Fr
Datasheets
1.PIC16F616T-ISL.pdf
(8 pages)
2.PIC16F688T-ISL.pdf
(688 pages)
3.PIC16C770-ISO.pdf
(8 pages)
4.PIC16F873A-ISO.pdf
(234 pages)
5.PIC16F873A-ISO.pdf
(6 pages)
6.PIC16F873A-ISO.pdf
(4 pages)
7.PIC16F873A-ISO.pdf
(6 pages)
8.PIC16F873A-ISO.pdf
(4 pages)
9.PIC16F873A-ISO.pdf
(22 pages)
Specifications of PIC16F876A-I/SO
Program Memory Type
FLASH
Program Memory Size
14KB (8K x 14)
Package / Case
28-SOIC (7.5mm Width)
Core Processor
PIC
Core Size
8-Bit
Speed
20MHz
Connectivity
I²C, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, POR, PWM, WDT
Number Of I /o
22
Eeprom Size
256 x 8
Ram Size
368 x 8
Voltage - Supply (vcc/vdd)
4 V ~ 5.5 V
Data Converters
A/D 5x10b
Oscillator Type
External
Operating Temperature
-40°C ~ 85°C
Processor Series
PIC16F
Core
PIC
Data Bus Width
8 bit
Data Ram Size
368 B
Interface Type
CCP, I2C, MSSP, SPI, USART
Maximum Clock Frequency
20 MHz
Number Of Programmable I/os
22
Number Of Timers
3
Operating Supply Voltage
2 V to 5.5 V
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
3rd Party Development Tools
52715-96, 52716-328, 52717-734
Development Tools By Supplier
PG164130, DV164035, DV244005, DV164005, PG164120, ICE2000, DM163022, DV164120
Minimum Operating Temperature
- 40 C
On-chip Adc
10 bit, 5 Channel
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
For Use With
XLT28SO-1 - SOCKET TRANSITION 28SOIC 300MIL309-1073 - ADAPTER 28-SOIC TO 28-SOIC309-1024 - ADAPTER 28-SOIC TO 28-DIP309-1023 - ADAPTER 28-SOIC TO 28-DIP
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
Other names
PIC16F876AI/SO
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
PIC16F876A-I/SO
Manufacturer:
IDT
Quantity:
201
- PIC16F616T-ISL PDF datasheet
- PIC16F688T-ISL PDF datasheet #2
- PIC16C770-ISO PDF datasheet #3
- PIC16F873A-ISO PDF datasheet #4
- PIC16F873A-ISO PDF datasheet #5
- PIC16F873A-ISO PDF datasheet #6
- PIC16F873A-ISO PDF datasheet #7
- PIC16F873A-ISO PDF datasheet #8
- PIC16F873A-ISO PDF datasheet #9
- Current page: 347 of 688
- Download datasheet (3Mb)
18.4.2
1997 Microchip Technology Inc.
RX/DT
USART Asynchronous Receiver
Baud Rate Generator
x64 Baud Rate CLK
SPBRG
Pin Buffer
and Control
The receiver block diagram is shown in
drives the data recovery block. The data recovery block is actually a high speed shifter operating
at x16 times the baud rate, whereas the main receive serial shifter operates at the bit rate or at
F
Once Asynchronous mode is selected, reception is enabled by setting the CREN bit
(RCSTA<4>).
The heart of the receiver is the receive (serial) shift register (RSR). After sampling the RX/TX pin
for the STOP bit, the received data in the RSR is transferred to the RCREG register (if it is empty).
If the transfer is complete, the RCIF flag bit is set. The actual interrupt can be enabled/disabled
by setting/clearing the RCIE enable bit. The RCIF flag bit is a read only bit which is cleared by
the hardware. It is cleared when the RCREG register has been read and is empty. The RCREG
is a double buffered register, i.e. it is a two deep FIFO. It is possible for two bytes of data to be
received and transferred to the RCREG FIFO and a third byte begin shifting to the RSR register.
On the detection of the STOP bit of the third byte, if the RCREG register is still full then overrun
error bit, OERR (RCSTA<1>), will be set. The word in the RSR will be lost. The RCREG register
can be read twice to retrieve the two bytes in the FIFO. The OERR bit has to be cleared in soft-
ware. This is done by resetting the receive logic (the CREN bit is cleared and then set). If the
OERR bit is set, transfers from the RSR register to the RCREG register are inhibited, so it is
essential to clear the OERR bit if it is set. Framing error bit, FERR (RCSTA<2>), is set if a stop
bit is detected as a low level. The FERR bit and the 9th receive bit are buffered the same way as
the receive data. Reading the RCREG will load the RX9D and FERR bits with new values, there-
fore it is essential for the user to read the RCSTA register before reading the next RCREG reg-
ister in order not to lose the old (previous) information in the FERR and RX9D bits.
Figure 18-4:
SPEN
OSC
.
USART Receive Block Diagram
Data
Recovery
Interrupt
CREN
Figure
RCIF
RCIE
RX9
Section 18. USART
18-4. The data is received on the RX/DT pin and
MSb
Stop
RX9D
(8)
OERR
7
RSR register
RCREG register
8
Data Bus
DS31018A-page 18-11
1
FERR
0
Start
LSb
FIFO
18
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