PIC16F876A-I/SO Microchip Technology, PIC16F876A-I/SO Datasheet - Page 270
![IC MCU FLASH 8KX14 EE 28SOIC](/photos/6/59/65909/150-28-soic_sml.jpg)
PIC16F876A-I/SO
Manufacturer Part Number
PIC16F876A-I/SO
Description
IC MCU FLASH 8KX14 EE 28SOIC
Manufacturer
Microchip Technology
Series
PIC® 16Fr
Datasheets
1.PIC16F616T-ISL.pdf
(8 pages)
2.PIC16F688T-ISL.pdf
(688 pages)
3.PIC16C770-ISO.pdf
(8 pages)
4.PIC16F873A-ISO.pdf
(234 pages)
5.PIC16F873A-ISO.pdf
(6 pages)
6.PIC16F873A-ISO.pdf
(4 pages)
7.PIC16F873A-ISO.pdf
(6 pages)
8.PIC16F873A-ISO.pdf
(4 pages)
9.PIC16F873A-ISO.pdf
(22 pages)
Specifications of PIC16F876A-I/SO
Program Memory Type
FLASH
Program Memory Size
14KB (8K x 14)
Package / Case
28-SOIC (7.5mm Width)
Core Processor
PIC
Core Size
8-Bit
Speed
20MHz
Connectivity
I²C, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, POR, PWM, WDT
Number Of I /o
22
Eeprom Size
256 x 8
Ram Size
368 x 8
Voltage - Supply (vcc/vdd)
4 V ~ 5.5 V
Data Converters
A/D 5x10b
Oscillator Type
External
Operating Temperature
-40°C ~ 85°C
Processor Series
PIC16F
Core
PIC
Data Bus Width
8 bit
Data Ram Size
368 B
Interface Type
CCP, I2C, MSSP, SPI, USART
Maximum Clock Frequency
20 MHz
Number Of Programmable I/os
22
Number Of Timers
3
Operating Supply Voltage
2 V to 5.5 V
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
3rd Party Development Tools
52715-96, 52716-328, 52717-734
Development Tools By Supplier
PG164130, DV164035, DV244005, DV164005, PG164120, ICE2000, DM163022, DV164120
Minimum Operating Temperature
- 40 C
On-chip Adc
10 bit, 5 Channel
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
For Use With
XLT28SO-1 - SOCKET TRANSITION 28SOIC 300MIL309-1073 - ADAPTER 28-SOIC TO 28-SOIC309-1024 - ADAPTER 28-SOIC TO 28-DIP309-1023 - ADAPTER 28-SOIC TO 28-DIP
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
Other names
PIC16F876AI/SO
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
PIC16F876A-I/SO
Manufacturer:
IDT
Quantity:
201
- PIC16F616T-ISL PDF datasheet
- PIC16F688T-ISL PDF datasheet #2
- PIC16C770-ISO PDF datasheet #3
- PIC16F873A-ISO PDF datasheet #4
- PIC16F873A-ISO PDF datasheet #5
- PIC16F873A-ISO PDF datasheet #6
- PIC16F873A-ISO PDF datasheet #7
- PIC16F873A-ISO PDF datasheet #8
- PIC16F873A-ISO PDF datasheet #9
- Current page: 270 of 688
- Download datasheet (3Mb)
PICmicro MID-RANGE MCU FAMILY
16.4.1.3
16.4.1.4
DS31016A-page 16-20
SDA
SCL
SSPIF
BF (SSPSTAT<0>)
CKP (SSPCON<4>)
S
Transmission
Clock Arbitration
A7
1
Data in
sampled
A6
2
When the R/W bit of the incoming address byte is set and an address match occurs, the R/W bit
of the SSPSTAT register is set. The received address is loaded into the SSPBUF register. The
ACK pulse will be sent on the ninth bit, and the SCL pin is held low. The transmit data must be
loaded into the SSPBUF register, which also loads the SSPSR register. Then the SCL pin should
be enabled by setting the CKP bit (SSPCON<4>). The master must monitor the SCL pin prior to
asserting another clock pulse. The slave devices may be holding off the master by stretching the
clock. The eight data bits are shifted out on the falling edge of the SCL input. This ensures that
the SDA signal is valid during the SCL high time
An SSP interrupt is generated for each data transfer byte. The SSPIF flag bit must be cleared in
software, and the SSPSTAT register is used to determine the status of the byte transfer. The
SSPIF flag bit is set on the falling edge of the ninth clock pulse.
As a slave-transmitter, the ACK pulse from the master-receiver is latched on the rising edge of
the ninth SCL input pulse. If the SDA line was high (not ACK), then the data transfer is complete.
When the not ACK is latched by the slave, the slave logic is reset and the slave then monitors for
another occurrence of the START bit. If the SDA line was low (ACK), the transmit data must be
loaded into the SSPBUF register, which also loads the SSPSR register. Then the SCL pin should
be enabled by setting the CKP bit.
Figure 16-9: I
Clock arbitration has the SCL pin to inhibit the master device from sending the next clock pulse.
The SSP module in I
to the SSP interrupt (SSPIF bit is set and the CKP bit is cleared). The data that needs to be trans-
mitted will need to be written to the SSPBUF register, and then the CKP bit will need to be set to
allow the master to generate the required clocks.
A5
Receiving Address
3
A4
4
A3
5
2
C Waveforms for Transmission (7-bit Address)
A2
6
A1
7
2
C slave mode will hold the SCL pin low when the CPU needs to respond
R/W = 1
8
9
ACK
responds to SSPIF
SCL held low
while CPU
D7
1
SSPBUF is written in software
(Figure
D6
cleared in software
2
Set bit after writing to SSPBUF
D5
3
16-9).
D4
4
Transmitting Data
D3
5
1997 Microchip Technology Inc.
D2
6
From SSP interrupt
service routine
D1
7
D0
8
ACK
9
P
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