PIC18F8390-I/PT Microchip Technology, PIC18F8390-I/PT Datasheet - Page 231
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PIC18F8390-I/PT
Manufacturer Part Number
PIC18F8390-I/PT
Description
IC PIC MCU FLASH 4KX16 80TQFP
Manufacturer
Microchip Technology
Series
PIC® 18Fr
Datasheets
1.PIC16F616T-ISL.pdf
(8 pages)
2.PIC18F6310-IPT.pdf
(28 pages)
3.PIC18F6390-IPT.pdf
(414 pages)
4.PIC18F6390-IPT.pdf
(16 pages)
5.PIC18F6390-IPT.pdf
(12 pages)
6.PIC18F6390-IPT.pdf
(6 pages)
7.PIC18F6390-IPT.pdf
(4 pages)
8.PIC18F8490-IPT.pdf
(412 pages)
Specifications of PIC18F8390-I/PT
Program Memory Type
FLASH
Program Memory Size
8KB (4K x 16)
Package / Case
80-TFQFP
Core Processor
PIC
Core Size
8-Bit
Speed
40MHz
Connectivity
I²C, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, HLVD, LCD, POR, PWM, WDT
Number Of I /o
66
Ram Size
768 x 8
Voltage - Supply (vcc/vdd)
4.2 V ~ 5.5 V
Data Converters
A/D 12x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Processor Series
PIC18F
Core
PIC
Data Bus Width
8 bit
Data Ram Size
768 B
Interface Type
SPI, I2C, EUSART, AUSART
Maximum Clock Frequency
40 MHz
Number Of Programmable I/os
66
Number Of Timers
4
Operating Supply Voltage
4.2 V to 5.5 V
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
3rd Party Development Tools
52715-96, 52716-328, 52717-734, 52712-325, EWPIC18
Development Tools By Supplier
PG164130, DV164035, DV244005, DV164005, PG164120, ICE2000, ICE4000, DV164136, DM163028
Minimum Operating Temperature
- 40 C
On-chip Adc
10 bit
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
For Use With
XLT80PT3 - SOCKET TRAN ICE 80MQFP/TQFPDM163028 - BOARD DEMO PICDEM LCDAC164320 - MODULE SKT MPLAB PM3 80TQFPAC174011 - MODULE SKT PROMATEII 80TQFP
Eeprom Size
-
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
PIC18F8390-I/PT
Manufacturer:
Microchip Technology
Quantity:
10 000
Part Number:
PIC18F8390-I/PT
Manufacturer:
MICRO
Quantity:
20 000
- PIC16F616T-ISL PDF datasheet
- PIC18F6310-IPT PDF datasheet #2
- PIC18F6390-IPT PDF datasheet #3
- PIC18F6390-IPT PDF datasheet #4
- PIC18F6390-IPT PDF datasheet #5
- PIC18F6390-IPT PDF datasheet #6
- PIC18F6390-IPT PDF datasheet #7
- PIC18F8490-IPT PDF datasheet #8
- Current page: 231 of 412
- Download datasheet (8Mb)
17.4
Synchronous Slave mode is entered by clearing bit
CSRC (TXSTA2<7>). This mode differs from the
Synchronous Master mode in that the shift clock is
supplied externally at the CK2 pin (instead of being
supplied internally in Master mode). This allows the
device to transfer or receive data while in any
low-power mode.
17.4.1
The operation of the Synchronous Master and Slave
modes are identical except in the case of the Sleep
mode.
If two words are written to the TXREG2 and then the
SLEEP instruction is executed, the following will occur:
a)
b)
c)
d)
e)
TABLE 17-8:
2004 Microchip Technology Inc.
INTCON
PIR3
PIE3
IPR3
RCSTA2
TXREG2
TXSTA2
SPBRG2
Legend: — = unimplemented, read as ‘0’. Shaded cells are not used for synchronous slave transmission.
Name
The first word will immediately transfer to the
TSR register and transmit.
The second word will remain in TXREG2
register.
Flag bit TX2IF will not be set.
When the first word has been shifted out of TSR,
the TXREG2 register will transfer the second
word to the TSR and flag bit TX2IF will now be
set.
If enable bit TX2IE is set, the interrupt will wake
the chip from Sleep. If the global interrupt is
enabled, the program will branch to the interrupt
vector.
AUSART Synchronous Slave Mode
AUSART SYNCHRONOUS
SLAVE TRANSMIT
AUSART2 Transmit Register
AUSART2 Baud Rate Generator Register Low Byte
GIE/GIEH PEIE/GIEL
CSRC
SPEN
Bit 7
REGISTERS ASSOCIATED WITH SYNCHRONOUS SLAVE TRANSMISSION
—
—
—
LCDIE
LCDIP
LCDIF
Bit 6
RX9
TX9
TMR0IE
RC2IE
RC2IP
RC2IF
SREN
TXEN
Bit 5
PIC18F6390/6490/8390/8490
Preliminary
INT0IE
TX2IF
TX2IE
TX2IP
CREN
SYNC
Bit 4
ADDEN
To set up a Synchronous Slave Transmission:
1.
2.
3.
4.
5.
6.
7.
8.
RBIE
Bit 3
—
—
—
—
Enable the synchronous slave serial port by
setting bits SYNC and SPEN and clearing bit
CSRC.
Clear bits CREN and SREN.
If interrupts are desired, set enable bit TX2IE.
If 9-bit transmission is desired, set bit TX9.
Enable the transmission by setting enable bit
TXEN.
If 9-bit transmission is selected, the ninth bit
should be loaded in bit TX9D.
Start transmission by loading data to the
TXREG2 register.
If using interrupts, ensure that the GIE and PEIE
bits in the INTCON register (INTCON<7:6>) are
set.
TMR0IF
BRGH
FERR
Bit 2
—
—
—
INT0IF
OERR
TRMT
Bit 1
—
—
—
RX9D
TX9D
DS39629B-page 229
RBIF
Bit 0
—
—
—
on Page
Values
Reset
59
61
61
61
63
63
63
63
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