PIC18F8390-I/PT Microchip Technology, PIC18F8390-I/PT Datasheet - Page 192
![no-image](/images/manufacturer_photos/0/4/439/microchip_technology_sml.jpg)
PIC18F8390-I/PT
Manufacturer Part Number
PIC18F8390-I/PT
Description
IC PIC MCU FLASH 4KX16 80TQFP
Manufacturer
Microchip Technology
Series
PIC® 18Fr
Datasheets
1.PIC16F616T-ISL.pdf
(8 pages)
2.PIC18F6310-IPT.pdf
(28 pages)
3.PIC18F6390-IPT.pdf
(414 pages)
4.PIC18F6390-IPT.pdf
(16 pages)
5.PIC18F6390-IPT.pdf
(12 pages)
6.PIC18F6390-IPT.pdf
(6 pages)
7.PIC18F6390-IPT.pdf
(4 pages)
8.PIC18F8490-IPT.pdf
(412 pages)
Specifications of PIC18F8390-I/PT
Program Memory Type
FLASH
Program Memory Size
8KB (4K x 16)
Package / Case
80-TFQFP
Core Processor
PIC
Core Size
8-Bit
Speed
40MHz
Connectivity
I²C, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, HLVD, LCD, POR, PWM, WDT
Number Of I /o
66
Ram Size
768 x 8
Voltage - Supply (vcc/vdd)
4.2 V ~ 5.5 V
Data Converters
A/D 12x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Processor Series
PIC18F
Core
PIC
Data Bus Width
8 bit
Data Ram Size
768 B
Interface Type
SPI, I2C, EUSART, AUSART
Maximum Clock Frequency
40 MHz
Number Of Programmable I/os
66
Number Of Timers
4
Operating Supply Voltage
4.2 V to 5.5 V
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
3rd Party Development Tools
52715-96, 52716-328, 52717-734, 52712-325, EWPIC18
Development Tools By Supplier
PG164130, DV164035, DV244005, DV164005, PG164120, ICE2000, ICE4000, DV164136, DM163028
Minimum Operating Temperature
- 40 C
On-chip Adc
10 bit
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
For Use With
XLT80PT3 - SOCKET TRAN ICE 80MQFP/TQFPDM163028 - BOARD DEMO PICDEM LCDAC164320 - MODULE SKT MPLAB PM3 80TQFPAC174011 - MODULE SKT PROMATEII 80TQFP
Eeprom Size
-
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
PIC18F8390-I/PT
Manufacturer:
Microchip Technology
Quantity:
10 000
Part Number:
PIC18F8390-I/PT
Manufacturer:
MICRO
Quantity:
20 000
- PIC16F616T-ISL PDF datasheet
- PIC18F6310-IPT PDF datasheet #2
- PIC18F6390-IPT PDF datasheet #3
- PIC18F6390-IPT PDF datasheet #4
- PIC18F6390-IPT PDF datasheet #5
- PIC18F6390-IPT PDF datasheet #6
- PIC18F6390-IPT PDF datasheet #7
- PIC18F8490-IPT PDF datasheet #8
- Current page: 192 of 412
- Download datasheet (8Mb)
PIC18F6390/6490/8390/8490
15.4.12
An Acknowledge sequence is enabled by setting the
Acknowledge
(SSPCON2<4>). When this bit is set, the SCL pin is
pulled low and the contents of the Acknowledge data bit
are presented on the SDA pin. If the user wishes to gen-
erate an Acknowledge, then the ACKDT bit should be
cleared. If not, the user should set the ACKDT bit before
starting an Acknowledge sequence. The Baud Rate
Generator then counts for one rollover period (T
and the SCL pin is deasserted (pulled high). When the
SCL pin is sampled high (clock arbitration), the Baud
Rate Generator counts for T
pulled low. Following this, the ACKEN bit is automatically
cleared, the Baud Rate Generator is turned off and the
MSSP module then goes into Idle mode (Figure 15-23).
15.4.12.1
If the user writes the SSPBUF when an Acknowledge
sequence is in progress, then WCOL is set and the
contents of the buffer are unchanged (the write doesn’t
occur).
FIGURE 15-23:
FIGURE 15-24:
DS39629B-page 190
Note: T
Note: T
ACKNOWLEDGE SEQUENCE
TIMING
SCL
SDA
WCOL Status Flag
Sequence
Falling edge of
9th clock
SSPIF
Write to SSPCON2,
BRG
BRG
Acknowledge sequence starts here,
SDA
SCL
= one Baud Rate Generator period.
= one Baud Rate Generator period.
ACKNOWLEDGE SEQUENCE WAVEFORM
STOP CONDITION RECEIVE OR TRANSMIT MODE
ACK
set PEN
Set SSPIF at the end
of receive
BRG
ACKEN = 1, ACKDT = 0
Enable
. The SCL pin is then
write to SSPCON2
T
T
BRG
BRG
SDA asserted low before rising edge of clock
to setup Stop condition
bit,
8
D0
ACKEN
T
SCL brought high after T
BRG
BRG
Preliminary
)
Cleared in
software
P
T
SCL = 1 for T
after SDA sampled high. P bit (SSPSTAT<4>) is set.
BRG
T
BRG
ACK
15.4.13
A Stop bit is asserted on the SDA pin at the end of a
receive/transmit by setting the Stop Sequence Enable
bit, PEN (SSPCON2<2>). At the end of a receive/
transmit, the SCL line is held low after the falling edge
of the ninth clock. When the PEN bit is set, the master
will assert the SDA line low. When the SDA line is
sampled low, the Baud Rate Generator is reloaded and
counts down to ‘0’. When the Baud Rate Generator
times out, the SCL pin will be brought high and one
T
SDA pin will be deasserted. When the SDA pin is sam-
pled high while SCL is high, the P bit (SSPSTAT<4>) is
set. A T
bit is set (Figure 15-24).
15.4.13.1
If the user writes the SSPBUF when a Stop sequence
is in progress, then the WCOL bit is set and the
contents of the buffer are unchanged (the write doesn’t
occur).
BRG
PEN bit (SSPCON2<2>) is cleared by
T
hardware and the SSPIF bit is set
BRG
9
BRG
BRG
(Baud Rate Generator rollover count) later, the
Set SSPIF at the end
of Acknowledge sequence
BRG
, followed by SDA = 1 for T
STOP CONDITION TIMING
later, the PEN bit is cleared and the SSPIF
WCOL Status Flag
ACKEN automatically cleared
2004 Microchip Technology Inc.
Cleared in
software
BRG
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