AT32UC3B1128-AUR Atmel, AT32UC3B1128-AUR Datasheet - Page 323
![MCU AVR32 128K FLASH 48-TQFP](/photos/6/82/68248/313-48-vqfp_sml.jpg)
AT32UC3B1128-AUR
Manufacturer Part Number
AT32UC3B1128-AUR
Description
MCU AVR32 128K FLASH 48-TQFP
Manufacturer
Atmel
Series
AVR®32 UC3r
Datasheet
1.AT32UC3B164-AUR.pdf
(680 pages)
Specifications of AT32UC3B1128-AUR
Package / Case
48-TQFP, 48-VQFP
Voltage - Supply (vcc/vdd)
1.65 V ~ 1.95 V
Operating Temperature
-40°C ~ 85°C
Speed
60MHz
Number Of I /o
28
Core Processor
AVR
Program Memory Type
FLASH
Ram Size
32K x 8
Program Memory Size
128KB (128K x 8)
Data Converters
A/D 6x10b
Oscillator Type
Internal
Peripherals
Brown-out Detect/Reset, DMA, POR, PWM, WDT
Connectivity
I²C, IrDA, SPI, SSC, UART/USART, USB
Core Size
32-Bit
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
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21.6.3.12
21.6.3.13
32059J–12/2010
Framing Error
Transmit Break
Table 21-9.
The receiver is capable of detecting framing errors. A framing error happens when the stop bit of
a received character is detected at level 0. This can occur if the receiver and the transmitter are
fully desynchronized.
A framing error is reported on the FRAME bit of the Channel Status Register (CSR). The
FRAME bit is asserted in the middle of the stop bit as soon as the framing error is detected. It is
cleared by writing the Control Register (CR) with the RSTSTA bit at 1.
Figure 21-24. Framing Error Status
The user can request the transmitter to generate a break condition on the TXD line. A break con-
dition drives the TXD line low during at least one complete character. It appears the same as a
0x00 character sent with the parity and the stop bits at 0. However, the transmitter holds the
TXD line at least during one character until the user requests the break condition to be removed.
A break is transmitted by writing the Control Register (CR) with the STTBRK bit at 1. This can be
performed at any time, either while the transmitter is empty (no character in either the Shift Reg-
ister or in THR) or when a character is being transmitted. If a break is requested while a
character is being shifted out, the character is first completed before the TXD line is held low.
Once STTBRK command is requested further STTBRK commands are ignored until the end of
the break is completed.
The break condition is removed by writing CR with the STPBRK bit at 1. If the STPBRK is
requested before the end of the minimum break duration (one character, including start, data,
parity and stop bits), the transmitter ensures that the break condition completes.
Baud Rate
200000
Baud Rate
56000
57600
Maximum Time-out Period (Continued)
FRAME
RXRDY
Clock
Write
RXD
CR
Start
Bit
D0
D1
D2
D3
D4
Bit Time
D5
18
17
5
D6
D7
Parity
Bit
Stop
Bit
RSTSTA = 1
AT32UC3B
Time-out
1 170
1 138
328
323
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