AT32UC3B1128-AUR Atmel, AT32UC3B1128-AUR Datasheet - Page 225
![MCU AVR32 128K FLASH 48-TQFP](/photos/6/82/68248/313-48-vqfp_sml.jpg)
AT32UC3B1128-AUR
Manufacturer Part Number
AT32UC3B1128-AUR
Description
MCU AVR32 128K FLASH 48-TQFP
Manufacturer
Atmel
Series
AVR®32 UC3r
Datasheet
1.AT32UC3B164-AUR.pdf
(680 pages)
Specifications of AT32UC3B1128-AUR
Package / Case
48-TQFP, 48-VQFP
Voltage - Supply (vcc/vdd)
1.65 V ~ 1.95 V
Operating Temperature
-40°C ~ 85°C
Speed
60MHz
Number Of I /o
28
Core Processor
AVR
Program Memory Type
FLASH
Ram Size
32K x 8
Program Memory Size
128KB (128K x 8)
Data Converters
A/D 6x10b
Oscillator Type
Internal
Peripherals
Brown-out Detect/Reset, DMA, POR, PWM, WDT
Connectivity
I²C, IrDA, SPI, SSC, UART/USART, USB
Core Size
32-Bit
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
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Figure 19-6. Master Write with One Data Byte
Figure 19-7. Master Write with Multiple Data Byte
Figure 19-8. Master Write with One Byte Internal Address and Multiple Data Bytes
32059J–12/2010
TXCOMP
TXCOMP
TXRDY
TXRDY
TWD
TWD
Write THR (Data n)
S
Write THR (Data n)
S
DADR
TXCOMP
DADR
TXRDY
TWD
The TWI transfers require the slave to acknowledge each received byte. During the acknowl-
edge clock pulse (9th pulse), the master releases the data line (HIGH), enabling the slave to pull
it down in order to generate the acknowledge. The master polls the data line during this clock
pulse and sets the NACK in the status register if the slave does not acknowledge the byte. As
with the other status bits, an interrupt can be generated if enabled in the interrupt enable register
(IER). If the slave acknowledges the byte, the data written in the THR, is then shifted in the inter-
nal shifter and transferred. When an acknowledge is detected, the TXRDY bit is set until a new
write in the THR. When no more data is written into the THR, the master generates a stop condi-
tion to end the transfer. The end of the complete transfer is marked by the TXCOMP bit set to
one. See
TXRDY is used as Transmit Ready for the Peripheral DMA Controller transmit channel.
W
Write THR (DATA)
S
W
A
Figure
DADR
IADR(7:0)
A
19-6,
Write THR (Data n+1)
DATA n
Figure
W
A
19-7, and
A
DATA n
Write THR (Data n+1)
A
DATA
Figure 19-8 on page
A
Write THR (Data n+x)
DATA n+5
Last data sent
(ACK received and TXRDY = 1)
A
Write THR (Data n+x)
STOP sent automaticaly
DATA n+5
Last data sent
P
A
225.
A
DATA n+x
(ACK received and TXRDY = 1)
(ACK received and TXRDY = 1)
STOP sent automaticaly
DATA n+x
STOP sent automaticaly
AT32UC3B
A
A
P
P
225
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