PIC18F67K90-I/MRRSL Microchip Technology, PIC18F67K90-I/MRRSL Datasheet - Page 445

PIC18F67K90-I/MRRSL

Manufacturer Part Number

PIC18F67K90-I/MRRSL

Description

MCU PIC 128K FLASH XLP 64QFN

Manufacturer

Microchip Technology

Series

PIC® XLP™ 18Fr

Datasheets

1.PIC18F65K90T-IPTRSL.pdf (566 pages)

2.PIC18F65K90T-IPTRSL.pdf (10 pages)

Specifications of PIC18F67K90-I/MRRSL

Core Size

8-Bit

Program Memory Size

128KB (64K x 16)

Core Processor

PIC

Speed

64MHz

Connectivity

I²C, LIN, SPI, UART/USART

Peripherals

Brown-out Detect/Reset, LCD, POR, PWM, WDT

Number Of I /o

Program Memory Type

FLASH

Eeprom Size

1K x 8

Ram Size

4K x 8

Voltage - Supply (vcc/vdd)

1.8 V ~ 5.5 V

Data Converters

A/D 16x12b

Oscillator Type

Internal

Operating Temperature

-40°C ~ 85°C

Package / Case

64-VFQFN, Exposed Pad

Controller Family/series

PIC18

Eeprom Memory Size

1024Byte

Ram Memory Size

3828Byte

Cpu Speed

16MIPS

No. Of Timers

Processor Series

PIC18F

Core

PIC

Data Bus Width

8 bit

Data Ram Size

4 KB

Interface Type

I2C, SPI, EUSART

Maximum Clock Frequency

64 MHz

Number Of Programmable I/os

Number Of Timers

Operating Supply Voltage

1.8 V to 5.5 V

Maximum Operating Temperature

+ 85 C

Mounting Style

SMD/SMT

3rd Party Development Tools

52715-96, 52716-328, 52717-734, 52712-325, EWPIC18

Development Tools By Supplier

DM163030, DM180021, DM183026-2, DM183032, DV164131, MA180027

Minimum Operating Temperature

- 40 C

On-chip Adc

12 bit, 16 Channel

Lead Free Status / RoHS Status

Lead free / RoHS Compliant

Lead Free Status / RoHS Status

Lead free / RoHS Compliant

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28.6

The user program memory is divided into four blocks

for the PIC18FX5K90 device and PIC18FX6K90

devices, and eight blocks for PIC18FX7K90 devices.

One of these is a boot block of 1 or 2 Kbytes. The

remainder of the memory is divided into blocks on

binary boundaries.

FIGURE 28-6:

 2010 Microchip Technology Inc.

Note 1: Sizes of memory areas are not to scale.

000000h

01FFFFh

200000h

3FFFFFh

Program Verification and

Code Protection

2: Boot block size is determined by the BBSIZ0 bit (CONFIG4L<4>).

Unimplemented

Code Memory

Configuration

Read as ‘

and ID

Space

CODE-PROTECTED PROGRAM MEMORY FOR THE PIC18F87K90 FAMILY

’

BBSIZ = 1 BBSIZ = 0 BBSIZ = 1 BBSIZ = 0 BBSIZ = 1 BBSIZ = 0

Block 0

Block 1

Block 2

Block 3

Block 4

Block 5

Block 6

Block 7

Block

2 kW

6 kW

8 kW

Boot

PIC18FX7K90

Preliminary

Block 0

Block 1

Block 2

Block 3

Block 4

Block 5

Block 6

Block 7

Block

7 kW

8 kW

Boot

PIC18F87K90 FAMILY

Each of the blocks has three code protection bits

associated with them. They are:

• Code-Protect bit (CPn)

• Write-Protect bit (WRTn)

• External Block Table Read bit (EBTRn)

Figure 28-6 shows the program memory organization for

48, 64, 96 and 128-Kbyte devices and the specific code

protection bit associated with each block. The actual

locations of the bits are summarized in Table 28-4.

Device/Memory Size

Block 0

Block 1

Block 2

Block 3

Block

2 kW

6 kW

8 kW

Boot

PIC18FX6K90

Block 0

Block 1

Block 2

Block 3

Block

7 kW

8 kW

Boot

Block 0

Block 1

Block 2

Block 3

Block

2 kW

4 kW

Boot

PIC18FX5K90

Block 0

Block 1

Block 2

Block 3

Block

3 kW

4 kW

Boot

DS39957B-page 445

0000h

0800h

1000h

17FFh

1800

3FFF

4000h

5FFFh

6000h

7FFF

8000h

BFFFh

C000h

FFFFh

10000h

13FFFh

14000h

17FFFh

18000h

1BFFFh

1C000h

1FFFFh

Address

PIC18F67K90-I/MRRSL Microchip Technology, PIC18F67K90-I/MRRSL Datasheet - Page 445

PIC18F67K90-I/MRRSL

Specifications of PIC18F67K90-I/MRRSL

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