PIC18F67K90-I/MRRSL Microchip Technology, PIC18F67K90-I/MRRSL Datasheet - Page 245

• Manufacturer Part Number: PIC18F67K90-I/MRRSL
• Description: MCU PIC 128K FLASH XLP 64QFN
• Manufacturer: Microchip Technology
• Series: PIC® XLP™ 18Fr

Specifications of PIC18F67K90-I/MRRSL

• Core Size: 8-Bit
• Program Memory Size: 128KB (64K x 16)
• Core Processor: PIC
• Speed: 64MHz
• Connectivity: I²C, LIN, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, LCD, POR, PWM, WDT
• Number Of I /o: 53
• Program Memory Type: FLASH
• Eeprom Size: 1K x 8
• Ram Size: 4K x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 5.5 V
• Data Converters: A/D 16x12b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 64-VFQFN, Exposed Pad
• Controller Family/series: PIC18
• Eeprom Memory Size: 1024Byte
• Ram Memory Size: 3828Byte
• Cpu Speed: 16MIPS
• No. Of Timers: 11
• Processor Series: PIC18F
• Core: PIC
• Data Bus Width: 8 bit
• Data Ram Size: 4 KB
• Interface Type: I2C, SPI, EUSART
• Maximum Clock Frequency: 64 MHz
• Number Of Programmable I/os: 53
• Number Of Timers: 11
• Operating Supply Voltage: 1.8 V to 5.5 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: 52715-96, 52716-328, 52717-734, 52712-325, EWPIC18
• Development Tools By Supplier: DM163030, DM180021, DM183026-2, DM183032, DV164131, MA180027
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 12 bit, 16 Channel
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

TABLE 18-5:
18.4
In Pulse-Width Modulation (PWM) mode, the CCP4 pin
produces up to a 10-bit resolution PWM output. Since
the CCP4 pin is multiplexed with a PORTC or PORTE
data latch, the appropriate TRIS bit must be cleared to
make the CCP4 pin an output.
Figure 18-3 shows a simplified block diagram of the
ECCP1 module in PWM mode.
For a step-by-step procedure on how to set up the CCP
module for PWM operation, see Section 18.4.3
“Setup for PWM Operation”.
 2010 Microchip Technology Inc.
CCP6CON
CCP7CON
CCP8CON
CCP9CON
CCP10CON
CCPTMRS1
CCPTMRS2
Legend: — = unimplemented, read as ‘0’. Shaded cells are not used by Capture/Compare or Timer1/3/5/7.
Note 1:
Note:
Name
PWM Mode
(1)
Unimplemented on devices with a program memory of 32 Kbytes (PIC18FX5K90).
Clearing the CCP4CON register will force
the RC1 or RE7 output latch (depending
on device configuration) to the default low
level. This is not the PORTC or PORTE
I/O data latch.
(1)
C7TSEL1 C7TSEL0
REGISTERS ASSOCIATED WITH CAPTURE, COMPARE, TIMER1/3/5/7 (CONTINUED)
Bit 7
—
—
—
—
—
—
Bit 6
—
—
—
—
—
—
DC10B1
DC6B1
DC7B1
DC8B1
DC9B1
Bit 5
—
—
C10TSEL0
C6TSEL0
Preliminary
DC10B0
DC6B0
DC7B0
DC8B0
DC9B0
Bit 4
PIC18F87K90 FAMILY
CCP10M3 CCP10M2 CCP10M1 CCP10M0
CCP6M3
CCP7M3
CCP8M3
CCP9M3
FIGURE 18-3:
Bit 3
Note 1:
2:
—
—
CCPR4H (Slave)
Duty Cycle Registers
Comparator
CCPR4L
TMR2
PR2
Comparator
The 8-bit TMR2 value is concatenated with the 2-bit
internal Q clock, or 2 bits of the prescaler, to create
the 10-bit time base.
CCP4 and its appropriate timers are used as an
example. For details on all of the CCP modules and
their timer assignments, see Table 18-2 and
Table 18-3.
C5TSEL0 C4TSEL1 C4TSEL0
C9TSEL0 C8TSEL1 C8TSEL0
CCP6M2 CCP6M1 CCP6M0
CCP7M2 CCP7M1 CCP7M0
CCP8M2 CCP8M1 CCP8M0
CCP9M2 CCP9M1 CCP9M0
Bit 2
(Note 1)
Clear Timer,
ECCP1 Pin and
latch D.C.
SIMPLIFIED PWM BLOCK
DIAGRAM
Bit 1
CCP4CON<5:4>
R
S
DS39957B-page 245
Bit 0
Q
TRISC<2>
RC2/ECCP1
on Page:
Values
Reset
80
80
78
78
79
79
79