PIC18F67K90-I/MRRSL Microchip Technology, PIC18F67K90-I/MRRSL Datasheet - Page 207

• Manufacturer Part Number: PIC18F67K90-I/MRRSL
• Description: MCU PIC 128K FLASH XLP 64QFN
• Manufacturer: Microchip Technology
• Series: PIC® XLP™ 18Fr

Specifications of PIC18F67K90-I/MRRSL

• Core Size: 8-Bit
• Program Memory Size: 128KB (64K x 16)
• Core Processor: PIC
• Speed: 64MHz
• Connectivity: I²C, LIN, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, LCD, POR, PWM, WDT
• Number Of I /o: 53
• Program Memory Type: FLASH
• Eeprom Size: 1K x 8
• Ram Size: 4K x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 5.5 V
• Data Converters: A/D 16x12b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 64-VFQFN, Exposed Pad
• Controller Family/series: PIC18
• Eeprom Memory Size: 1024Byte
• Ram Memory Size: 3828Byte
• Cpu Speed: 16MIPS
• No. Of Timers: 11
• Processor Series: PIC18F
• Core: PIC
• Data Bus Width: 8 bit
• Data Ram Size: 4 KB
• Interface Type: I2C, SPI, EUSART
• Maximum Clock Frequency: 64 MHz
• Number Of Programmable I/os: 53
• Number Of Timers: 11
• Operating Supply Voltage: 1.8 V to 5.5 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: 52715-96, 52716-328, 52717-734, 52712-325, EWPIC18
• Development Tools By Supplier: DM163030, DM180021, DM183026-2, DM183032, DV164131, MA180027
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 12 bit, 16 Channel
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

FIGURE 15-5:
15.5.5
When Timer3/5/7 gate value status is utilized, it is
possible to read the most current level of the gate con-
trol value. The value is stored in the TxGVAL bit
(TxGCON<2>). The TxGVAL bit is valid even when the
Timer3/5/7 gate is not enabled (TMRxGE bit is
cleared).
 2010 Microchip Technology Inc.
Timer3/5/7
TMRxGIF
TMRxGE
TxGSPM
TxDONE
TxGPOL
TxGGO/
TxGVAL
TxG_IN
TxGTM
TxCKI
TIMER3/5/7 GATE VALUE STATUS
TIMER3/5/7 GATE SINGLE PULSE AND TOGGLE COMBINED MODE
N
Cleared by Software
Set by Software
Counting Enabled on
Rising Edge of TxG
Preliminary
N + 1
PIC18F87K90 FAMILY
Falling Edge of TxGVAL
N + 2
15.5.6
When the Timer3/5/7 gate event interrupt is enabled, it
is possible to generate an interrupt upon the comple-
tion of a gate event. When the falling edge of TxGVAL
occurs, the TMRxGIF flag bit in the PIRx register will be
set. If the TMRxGIE bit in the PIEx register is set, then
an interrupt will be recognized.
The TMRxGIF flag bit operates even when the Timer3/
5/7 gate is not enabled (TMRxGE bit is cleared).
Set by Hardware on
N + 3
TIMER3/5/7 GATE EVENT
INTERRUPT
Cleared by Hardware on
Falling Edge of TxGVAL
N + 4
DS39957B-page 207
Cleared by
Software