PIC18F2580-E/SP Microchip Technology, PIC18F2580-E/SP Datasheet - Page 95
![IC PIC MCU FLASH 16KX16 28DIP](/photos/6/59/65908/150-28-dip_sml.jpg)
PIC18F2580-E/SP
Manufacturer Part Number
PIC18F2580-E/SP
Description
IC PIC MCU FLASH 16KX16 28DIP
Manufacturer
Microchip Technology
Series
PIC® 18Fr
Datasheets
1.PIC18F2221-ISO.pdf
(46 pages)
2.PIC18F4480-IPT.pdf
(490 pages)
3.PIC18F4480-IPT.pdf
(8 pages)
4.PIC18F4480-IPT.pdf
(6 pages)
5.PIC18F4480-IPT.pdf
(6 pages)
6.PIC18F2580-ESO.pdf
(483 pages)
Specifications of PIC18F2580-E/SP
Program Memory Type
FLASH
Program Memory Size
32KB (16K x 16)
Package / Case
28-DIP (0.300", 7.62mm)
Core Processor
PIC
Core Size
8-Bit
Speed
25MHz
Connectivity
CAN, I²C, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, HLVD, POR, PWM, WDT
Number Of I /o
25
Eeprom Size
256 x 8
Ram Size
1.5K x 8
Voltage - Supply (vcc/vdd)
4.2 V ~ 5.5 V
Data Converters
A/D 8x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 125°C
Processor Series
PIC18F
Core
PIC
Data Bus Width
8 bit
Data Ram Size
1.5 KB
Interface Type
SPI/I2C/MSSP/EUSART
Maximum Clock Frequency
40 MHz
Number Of Programmable I/os
25
Number Of Timers
4
Maximum Operating Temperature
+ 125 C
Mounting Style
Through Hole
3rd Party Development Tools
52715-96, 52716-328, 52717-734, 52712-325, EWPIC18
Development Tools By Supplier
PG164130, DV164035, DV244005, DV164005, PG164120, ICE2000, ICE4000, DM163011, DV164136
Minimum Operating Temperature
- 40 C
On-chip Adc
8-ch x 10-bit
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
For Use With
DVA18XP280 - DEVICE ADAPTER 18F2220 PDIP 28LD
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
PIC18F2580-E/SP
Manufacturer:
Microchip Technology
Quantity:
135
- PIC18F2221-ISO PDF datasheet
- PIC18F4480-IPT PDF datasheet #2
- PIC18F4480-IPT PDF datasheet #3
- PIC18F4480-IPT PDF datasheet #4
- PIC18F4480-IPT PDF datasheet #5
- PIC18F2580-ESO PDF datasheet #6
- Current page: 95 of 490
- Download datasheet (9Mb)
6.4
While the program memory can be addressed in only
one way – through the program counter – information
in the data memory space can be addressed in several
ways. For most instructions, the addressing mode is
fixed. Other instructions may use up to three modes,
depending on which operands are used and whether or
not the extended instruction set is enabled.
The addressing modes are:
• Inherent
• Literal
• Direct
• Indirect
An additional addressing mode, Indexed Literal Offset,
is available when the extended instruction set is
enabled (XINST Configuration bit = 1). Its operation is
discussed in greater detail in Section 6.6.1 “Indexed
Addressing with Literal Offset”.
6.4.1
Many PIC18 control instructions do not need any
argument at all; they either perform an operation that
globally affects the device or they operate implicitly on
one register. This addressing mode is known as
Inherent Addressing. Examples include SLEEP, RESET
and DAW.
Other instructions work in a similar way but require an
additional explicit argument in the opcode. This is
known as Literal Addressing mode because they
require some literal value as an argument. Examples
include ADDLW and MOVLW which, respectively, add or
move a literal value to the W register. Other examples
include CALL and GOTO, which include a 20-bit
program memory address.
6.4.2
Direct Addressing specifies all or part of the source
and/or destination address of the operation within the
opcode itself. The options are specified by the
arguments accompanying the instruction.
In the core PIC18 instruction set, bit-oriented and
byte-oriented instructions use some version of Direct
Addressing by default. All of these instructions include
some 8-bit literal address as their Least Significant
Byte. This address specifies either a register address in
one of the banks of data RAM (Section 6.3.3 “General
© 2009 Microchip Technology Inc.
Note:
Data Addressing Modes
The execution of some instructions in the
core PIC18 instruction set are changed
when the PIC18 extended instruction
set is enabled. See Section 6.6 “Data
Memory and the Extended Instruction
Set” for more information.
INHERENT AND LITERAL
ADDRESSING
DIRECT ADDRESSING
PIC18F2480/2580/4480/4580
Purpose Register File”) or a location in the Access
Bank (Section 6.3.2 “Access Bank”) as the data
source for the instruction.
The Access RAM bit ‘a’ determines how the address is
interpreted. When ‘a’ is ‘1’, the contents of the BSR
(Section 6.3.1 “Bank Select Register (BSR)”) are
used with the address to determine the complete 12-bit
address of the register. When ‘a’ is ‘0’, the address is
interpreted as being a register in the Access Bank.
Addressing that uses the Access RAM is sometimes
also known as Direct Forced Addressing mode.
A few instructions, such as MOVFF, include the entire
12-bit address (either source or destination) in their
opcodes. In these cases, the BSR is ignored entirely.
The destination of the operation’s results is determined
by the destination bit, ‘d’. When ‘d’ is ‘1’, the results are
stored back in the source register, overwriting its origi-
nal contents. When ‘d’ is ‘0’, the results are stored in
the W register. Instructions without the ‘d’ argument
have a destination that is implicit in the instruction; their
destination is either the target register being operated
on or the W register.
6.4.3
Indirect Addressing allows the user to access a location
in data memory without giving a fixed address in the
instruction. This is done by using File Select Registers
(FSRs) as pointers to the locations to be read or written
to. Since the FSRs are themselves located in RAM as
Special File Registers, they can also be directly manip-
ulated under program control. This makes FSRs very
useful in implementing data structures, such as tables
and arrays in data memory.
The registers for Indirect Addressing are also imple-
mented with Indirect File Operands (INDFs) that permit
automatic manipulation of the pointer value with
auto-incrementing, auto-decrementing or offsetting
with another value. This allows for efficient code, using
loops, such as the example of clearing an entire RAM
bank in Example 6-5.
EXAMPLE 6-5:
NEXT
CONTINUE
LFSR
CLRF
BTFSS
BRA
INDIRECT ADDRESSING
FSR0, 100h ;
POSTINC0
FSR0H,1
NEXT
HOW TO CLEAR RAM
(BANK 1) USING
INDIRECT ADDRESSING
; Clear INDF
; register then
; inc pointer
; All done with
; Bank1?
; NO, clear next
; YES, continue
DS39637D-page 95
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