PIC18F2580-E/SP Microchip Technology, PIC18F2580-E/SP Datasheet - Page 341
![IC PIC MCU FLASH 16KX16 28DIP](/photos/6/59/65908/150-28-dip_sml.jpg)
PIC18F2580-E/SP
Manufacturer Part Number
PIC18F2580-E/SP
Description
IC PIC MCU FLASH 16KX16 28DIP
Manufacturer
Microchip Technology
Series
PIC® 18Fr
Datasheets
1.PIC18F2221-ISO.pdf
(46 pages)
2.PIC18F4480-IPT.pdf
(490 pages)
3.PIC18F4480-IPT.pdf
(8 pages)
4.PIC18F4480-IPT.pdf
(6 pages)
5.PIC18F4480-IPT.pdf
(6 pages)
6.PIC18F2580-ESO.pdf
(483 pages)
Specifications of PIC18F2580-E/SP
Program Memory Type
FLASH
Program Memory Size
32KB (16K x 16)
Package / Case
28-DIP (0.300", 7.62mm)
Core Processor
PIC
Core Size
8-Bit
Speed
25MHz
Connectivity
CAN, I²C, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, HLVD, POR, PWM, WDT
Number Of I /o
25
Eeprom Size
256 x 8
Ram Size
1.5K x 8
Voltage - Supply (vcc/vdd)
4.2 V ~ 5.5 V
Data Converters
A/D 8x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 125°C
Processor Series
PIC18F
Core
PIC
Data Bus Width
8 bit
Data Ram Size
1.5 KB
Interface Type
SPI/I2C/MSSP/EUSART
Maximum Clock Frequency
40 MHz
Number Of Programmable I/os
25
Number Of Timers
4
Maximum Operating Temperature
+ 125 C
Mounting Style
Through Hole
3rd Party Development Tools
52715-96, 52716-328, 52717-734, 52712-325, EWPIC18
Development Tools By Supplier
PG164130, DV164035, DV244005, DV164005, PG164120, ICE2000, ICE4000, DM163011, DV164136
Minimum Operating Temperature
- 40 C
On-chip Adc
8-ch x 10-bit
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
For Use With
DVA18XP280 - DEVICE ADAPTER 18F2220 PDIP 28LD
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
PIC18F2580-E/SP
Manufacturer:
Microchip Technology
Quantity:
135
- PIC18F2221-ISO PDF datasheet
- PIC18F4480-IPT PDF datasheet #2
- PIC18F4480-IPT PDF datasheet #3
- PIC18F4480-IPT PDF datasheet #4
- PIC18F4480-IPT PDF datasheet #5
- PIC18F2580-ESO PDF datasheet #6
- Current page: 341 of 490
- Download datasheet (9Mb)
24.9.2
As already mentioned, the Time Quanta is a fixed unit
derived from the oscillator period and baud rate
prescaler. Its relationship to T
Rate is shown in Example 24-6.
EXAMPLE 24-6:
The frequencies of the oscillators in the different nodes
must be coordinated in order to provide a system wide
specified nominal bit time. This means that all oscilla-
tors must have a T
It should also be noted that although the number of T
is programmable from 4 to 25, the usable minimum is
8 T
8 T
© 2009 Microchip Technology Inc.
T
T
Nominal Bit Rate (bits/s) = 1/T
This frequency (F
frequency used. If, for example, a 10 MHz external
signal is used along with a PLL, then the effective
frequency will be 4 x 10 MHz which equals 40 MHz.
CASE 1:
For F
Nominal Bit Time = 8 T
T
T
Nominal Bit Rate = 1/10
CASE 2:
For F
Nominal Bit Time = 8 T
T
T
Nominal Bit Rate = 1/1.6 * 10
CASE 3:
For F
Nominal Bit Time = 25 T
T
T
Nominal Bit Rate = 1/1.28 * 10
Q
BIT
Q
BIT
Q
BIT
Q
BIT
Q
Q
= (2 * 1)/16 = 0.125 μs (125 ns)
= (2 * 2)/20 = 0.2 μs (200 ns)
= (2 * 64)/25 = 5.12 μs
. There is no assurance that a bit time of less than
(μs) = (2 * (BRP+1))/F
in length will operate correctly.
(μs) = T
= 8 * 0.125 = 1 μs (10
= 8 * 0.2 = 1.6 μs (1.6 * 10
= 25 * 5.12 = 128 μs (1.28 * 10
OSC
OSC
OSC
= 16 MHz, BRP<5:0> = 00h and
= 20 MHz, BRP<5:0> = 01h and
= 25 MHz, BRP<5:0> = 3Fh and
TIME QUANTA
Q
(μs) * number of T
OSC
OSC
CALCULATING T
NOMINAL BIT RATE AND
NOMINAL BIT TIME
that is an integral divisor of T
-6
Q
Q
) refers to the effective
OSC
= 10
Q
:
:
-6
:
s)
-6
BIT
(MHz)
6
-4
BIT
s = 625,000 bits/s
-6
bits/s (1 Mb/s)
= 7813 bits/s
s)
Q
and the Nominal Bit
per bit interval
-4
(625 Kb/s)
(7.8 Kb/s)
s)
Q
,
PIC18F2480/2580/4480/4580
Q
Q
.
24.9.3
This part of the bit time is used to synchronize the
various CAN nodes on the bus. The edge of the input
signal is expected to occur during the sync segment.
The duration is 1 T
24.9.4
This part of the bit time is used to compensate for phys-
ical delay times within the network. These delay times
consist of the signal propagation time on the bus line
and the internal delay time of the nodes. The length of
the propagation segment can be programmed from
1 T
24.9.5
The phase buffer segments are used to optimally
locate the sampling point of the received bit within the
nominal bit time. The sampling point occurs between
Phase Segment 1 and Phase Segment 2. These
segments can be lengthened or shortened by the
resynchronization
Segment 1 determines the sampling point within a bit
time. Phase Segment 1 is programmable from 1 T
8 T
before the next transmitted data transition and is also
programmable from 1 T
due to IPT requirements, the actual minimum length of
Phase Segment 2 is 2 T
equal to the greater of Phase Segment 1 or the
Information Processing Time (IPT). The sampling point
should be as late as possible or approximately 80% of
the bit time.
24.9.6
The sample point is the point of time at which the bus
level is read and the value of the received bit is deter-
mined. The sampling point occurs at the end of Phase
Segment 1. If the bit timing is slow and contains many
T
line at the sample point. The value of the received bit is
determined to be the value of the majority decision of
three values. The three samples are taken at the sam-
ple point and twice before, with a time of T
each sample.
24.9.7
The Information Processing Time (IPT) is the time
segment starting at the sample point that is reserved
for calculation of the subsequent bit level. The CAN
specification defines this time to be less than or equal
to 2 T
define this time to be 2 T
must be at least 2 T
Q
, it is possible to specify multiple sampling of the bus
Q
Q
to 8 T
in duration. Phase Segment 2 provides a delay
Q
. The PIC18F2480/2580/4480/4580 devices
Q
SYNCHRONIZATION SEGMENT
PROPAGATION SEGMENT
PHASE BUFFER SEGMENTS
SAMPLE POINT
INFORMATION PROCESSING TIME
by setting the PRSEG<2:0> bits.
Q
Q
.
process.
long.
Q
Q
to 8 T
Q
, or it may be defined to be
. Thus, Phase Segment 2
The
Q
in duration. However,
DS39637D-page 341
end
Q
/2 between
of
Phase
Q
to
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