PIC18F2580-E/SP Microchip Technology, PIC18F2580-E/SP Datasheet - Page 221
![IC PIC MCU FLASH 16KX16 28DIP](/photos/6/59/65908/150-28-dip_sml.jpg)
PIC18F2580-E/SP
Manufacturer Part Number
PIC18F2580-E/SP
Description
IC PIC MCU FLASH 16KX16 28DIP
Manufacturer
Microchip Technology
Series
PIC® 18Fr
Datasheets
1.PIC18F2221-ISO.pdf
(46 pages)
2.PIC18F4480-IPT.pdf
(490 pages)
3.PIC18F4480-IPT.pdf
(8 pages)
4.PIC18F4480-IPT.pdf
(6 pages)
5.PIC18F4480-IPT.pdf
(6 pages)
6.PIC18F2580-ESO.pdf
(483 pages)
Specifications of PIC18F2580-E/SP
Program Memory Type
FLASH
Program Memory Size
32KB (16K x 16)
Package / Case
28-DIP (0.300", 7.62mm)
Core Processor
PIC
Core Size
8-Bit
Speed
25MHz
Connectivity
CAN, I²C, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, HLVD, POR, PWM, WDT
Number Of I /o
25
Eeprom Size
256 x 8
Ram Size
1.5K x 8
Voltage - Supply (vcc/vdd)
4.2 V ~ 5.5 V
Data Converters
A/D 8x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 125°C
Processor Series
PIC18F
Core
PIC
Data Bus Width
8 bit
Data Ram Size
1.5 KB
Interface Type
SPI/I2C/MSSP/EUSART
Maximum Clock Frequency
40 MHz
Number Of Programmable I/os
25
Number Of Timers
4
Maximum Operating Temperature
+ 125 C
Mounting Style
Through Hole
3rd Party Development Tools
52715-96, 52716-328, 52717-734, 52712-325, EWPIC18
Development Tools By Supplier
PG164130, DV164035, DV244005, DV164005, PG164120, ICE2000, ICE4000, DM163011, DV164136
Minimum Operating Temperature
- 40 C
On-chip Adc
8-ch x 10-bit
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
For Use With
DVA18XP280 - DEVICE ADAPTER 18F2220 PDIP 28LD
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
PIC18F2580-E/SP
Manufacturer:
Microchip Technology
Quantity:
135
- PIC18F2221-ISO PDF datasheet
- PIC18F4480-IPT PDF datasheet #2
- PIC18F4480-IPT PDF datasheet #3
- PIC18F4480-IPT PDF datasheet #4
- PIC18F4480-IPT PDF datasheet #5
- PIC18F2580-ESO PDF datasheet #6
- Current page: 221 of 490
- Download datasheet (9Mb)
18.4.10
Transmission of a data byte, a 7-bit address or the
other half of a 10-bit address is accomplished by simply
writing a value to the SSPBUF register. This action will
set the Buffer Full flag bit, BF, and allow the Baud Rate
Generator to begin counting and start the next trans-
mission. Each bit of address/data will be shifted out
onto the SDA pin after the falling edge of SCL is
asserted (see data hold time specification parameter
106). SCL is held low for one Baud Rate Generator roll-
over count (T
released high (see data setup time specification
parameter 107). When the SCL pin is released high, it
is held that way for T
must remain stable for that duration and some hold
time after the next falling edge of SCL. After the eighth
bit is shifted out (the falling edge of the eighth clock),
the BF flag is cleared and the master releases SDA.
This allows the slave device being addressed to
respond with an ACK bit during the ninth bit time if an
address match occurred, or if data was received
properly. The status of ACK is written into the ACKDT
bit on the falling edge of the ninth clock. If the master
receives an Acknowledge, the Acknowledge status bit,
ACKSTAT, is cleared. If not, the bit is set. After the ninth
clock, the SSPIF bit is set and the master clock (Baud
Rate Generator) is suspended until the next data byte
is loaded into the SSPBUF, leaving SCL low and SDA
unchanged (Figure 18-21).
After the write to the SSPBUF, each bit of address will
be shifted out on the falling edge of SCL until all seven
address bits and the R/W bit are completed. On the fall-
ing edge of the eighth clock, the master will deassert
the SDA pin, allowing the slave to respond with an
Acknowledge. On the falling edge of the ninth clock, the
master will sample the SDA pin to see if the address
was recognized by a slave. The status of the ACK bit is
loaded into the ACKSTAT status bit (SSPCON2<6>).
Following the falling edge of the ninth clock transmis-
sion of the address, the SSPIF flag is set, the BF flag is
cleared and the Baud Rate Generator is turned off until
another write to the SSPBUF takes place, holding SCL
low and allowing SDA to float.
18.4.10.1
In Transmit mode, the BF bit (SSPSTAT<0>) is set
when the CPU writes to SSPBUF and is cleared when
all 8 bits are shifted out.
18.4.10.2
If the user writes the SSPBUF when a transmit is
already in progress (i.e., SSPSR is still shifting out a
data byte), the WCOL is set and the contents of the buf-
fer are unchanged (the write doesn’t occur).
WCOL must be cleared in software.
© 2009 Microchip Technology Inc.
I
TRANSMISSION
2
BRG
C MASTER MODE
BF Status Flag
WCOL Status Flag
). Data should be valid before SCL is
BRG
. The data on the SDA pin
PIC18F2480/2580/4480/4580
18.4.10.3
In Transmit mode, the ACKSTAT bit (SSPCON2<6>) is
cleared when the slave has sent an Acknowledge
(ACK = 0) and is set when the slave does not Acknowl-
edge (ACK = 1). A slave sends an Acknowledge when
it has recognized its address (including a general call),
or when the slave has properly received its data.
18.4.11
Master mode reception is enabled by programming the
Receive Enable bit, RCEN (SSPCON2<3>).
The Baud Rate Generator begins counting and on each
rollover, the state of the SCL pin changes (high-to-low/
low-to-high) and data is shifted into the SSPSR. After
the falling edge of the eighth clock, the receive enable
flag is automatically cleared, the contents of the
SSPSR are loaded into the SSPBUF, the BF flag bit is
set, the SSPIF flag bit is set and the Baud Rate
Generator is suspended from counting, holding SCL
low. The MSSP is now in Idle state awaiting the next
command. When the buffer is read by the CPU, the BF
flag bit is automatically cleared. The user can then
send an Acknowledge bit at the end of reception by
setting the Acknowledge sequence enable bit, ACKEN
(SSPCON2<4>).
18.4.11.1
In receive operation, the BF bit is set when an address
or data byte is loaded into SSPBUF from SSPSR. It is
cleared when the SSPBUF register is read.
18.4.11.2
In receive operation, the SSPOV bit is set when 8 bits
are received into the SSPSR and the BF flag bit is
already set from a previous reception.
18.4.11.3
If the user writes the SSPBUF when a receive is
already in progress (i.e., SSPSR is still shifting in a data
byte), the WCOL bit is set and the contents of the buffer
are unchanged (the write doesn’t occur).
Note:
I
The MSSP module must be in an Idle state
before the RCEN bit is set or the RCEN bit
will be disregarded.
2
ACKSTAT Status Flag
C MASTER MODE RECEPTION
BF Status Flag
SSPOV Status Flag
WCOL Status Flag
DS39637D-page 221
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