PIC24FJ64GB002-I/ML Microchip Technology, PIC24FJ64GB002-I/ML Datasheet - Page 60

IC MCU 16BIT 64KB FLASH 28QFN

PIC24FJ64GB002-I/ML

Manufacturer Part Number
PIC24FJ64GB002-I/ML
Description
IC MCU 16BIT 64KB FLASH 28QFN
Manufacturer
Microchip Technology
Series
PIC® XLP™ 24Fr

Specifications of PIC24FJ64GB002-I/ML

Program Memory Type
FLASH
Program Memory Size
64KB (22K x 24)
Package / Case
28-VQFN Exposed Pad, 28-HVQFN, 28-SQFN, 28-DHVQFN
Core Processor
PIC
Core Size
16-Bit
Speed
32MHz
Connectivity
I²C, IrDA, SPI, UART/USART, USB OTG
Peripherals
Brown-out Detect/Reset, LVD, POR, PWM, WDT
Number Of I /o
19
Ram Size
8K x 8
Voltage - Supply (vcc/vdd)
2 V ~ 3.6 V
Data Converters
A/D 9x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Processor Series
PIC24FJ
Core
PIC
Data Bus Width
16 bit
Data Ram Size
8 KB
Interface Type
I2C/IrDA/SPI/UART
Maximum Clock Frequency
32 MHz
Number Of Programmable I/os
19
Number Of Timers
5
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
3rd Party Development Tools
52713-733, 52714-737, 53276-922, EWDSPIC
Development Tools By Supplier
PG164130, DV164035, DV244005, DV164005, PG164120, DM240001, DM240011
Minimum Operating Temperature
- 40 C
On-chip Adc
9-ch x 10-bit
Controller Family/series
PIC24
Ram Memory Size
8KB
Cpu Speed
32MHz
No. Of Timers
5
Embedded Interface Type
I2C, LIN, SPI, UART, USB
Rohs Compliant
Yes
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Lead Free Status / Rohs Status
Lead free / RoHS Compliant

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
PIC24FJ64GB002-I/ML
Manufacturer:
ANAREN
Quantity:
5 000
PIC24FJ64GB004 FAMILY
EXAMPLE 5-4:
EXAMPLE 5-5:
EXAMPLE 5-6:
DS39940D-page 60
// C example using MPLAB C30
//Set up NVMCON for row programming
//Set up pointer to the first memory location to be written
//Perform TBLWT instructions to write necessary number of latches
for(i=0; i < 2*NUM_INSTRUCTION_PER_ROW; i++)
// C example using MPLAB C30
asm("DISI #5");
__builtin_write_NVM();
#define NUM_INSTRUCTION_PER_ROW 64
unsigned int offset;
unsigned int i;
unsigned long progAddr = 0xXXXXXX;
unsigned int progData[2*NUM_INSTRUCTION_PER_ROW];
NVMCON = 0x4001;
TBLPAG = progAddr>>16;
offset = progAddr & 0xFFFF;
{
}
__builtin_tblwtl(offset, progData[i++]);
__builtin_tblwth(offset, progData[i]);
offset = offset + 2;
DISI
MOV
MOV
MOV
MOV
BSET
NOP
NOP
BTSC
BRA
#5
#0x55, W0
W0, NVMKEY
#0xAA, W1
W1, NVMKEY
NVMCON, #WR
NVMCON, #15
$-2
LOADING THE WRITE BUFFERS – ‘C’ LANGUAGE CODE
INITIATING A PROGRAMMING SEQUENCE – ASSEMBLY LANGUAGE CODE
INITIATING A PROGRAMMING SEQUENCE – ‘C’ LANGUAGE CODE
// Block all interrupts with priority < 7
// for next 5 instructions
// Perform unlock sequence and set WR
; Block all interrupts with priority <7
; for next 5 instructions
; Write the 55 key
;
; Write the AA key
; Start the erase sequence
;
;
; and wait for it to be
; completed
// Buffer of data to write
// Write to address low word
// Write to upper byte
// Address of row to write
// Initialize NVMCON
// Initialize PM Page Boundary SFR
// Initialize lower word of address
// Increment address
 2010 Microchip Technology Inc.

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