PIC24FJ64GB002-I/ML Microchip Technology, PIC24FJ64GB002-I/ML Datasheet - Page 123

• Manufacturer Part Number: PIC24FJ64GB002-I/ML
• Description: IC MCU 16BIT 64KB FLASH 28QFN
• Manufacturer: Microchip Technology
• Series: PIC® XLP™ 24Fr

Specifications of PIC24FJ64GB002-I/ML

• Program Memory Type: FLASH
• Program Memory Size: 64KB (22K x 24)
• Package / Case: 28-VQFN Exposed Pad, 28-HVQFN, 28-SQFN, 28-DHVQFN
• Core Processor: PIC
• Core Size: 16-Bit
• Speed: 32MHz
• Connectivity: I²C, IrDA, SPI, UART/USART, USB OTG
• Peripherals: Brown-out Detect/Reset, LVD, POR, PWM, WDT
• Number Of I /o: 19
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 2 V ~ 3.6 V
• Data Converters: A/D 9x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Processor Series: PIC24FJ
• Core: PIC
• Data Bus Width: 16 bit
• Data Ram Size: 8 KB
• Interface Type: I2C/IrDA/SPI/UART
• Maximum Clock Frequency: 32 MHz
• Number Of Programmable I/os: 19
• Number Of Timers: 5
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: 52713-733, 52714-737, 53276-922, EWDSPIC
• Development Tools By Supplier: PG164130, DV164035, DV244005, DV164005, PG164120, DM240001, DM240011
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 9-ch x 10-bit
• Controller Family/series: PIC24
• Ram Memory Size: 8KB
• Cpu Speed: 32MHz
• No. Of Timers: 5
• Embedded Interface Type: I2C, LIN, SPI, UART, USB
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

REGISTER 9-1:
 2010 Microchip Technology Inc.
bit 15
bit 7
Legend:
R = Readable bit
-n = Value at POR
HC = Hardware Clearable bit
bit 15
bit 14-2
bit 1
bit 0
Note 1:
R/W-0, HC
DSEN
U-0
—
2:
3:
(1)
These bits are reset only in the case of a POR event outside of Deep Sleep mode.
Reset value is ‘0’ for initial power-on POR only and ‘1’ for Deep Sleep POR.
This is a status bit only; a DSBOR event will NOT cause a wake-up from Deep Sleep.
DSEN: Deep Sleep Enable bit
1 = Device entered Deep Sleep when PWRSAV #0 was executed in the next instruction
0 = Device entered normal Sleep when PWRSAV #0 was executed
Unimplemented: Read as ‘0’
DSBOR: Deep Sleep BOR Event Status bit
1 = The DSBOR is active and a BOR event is detected during Deep Sleep
0 = The DSBOR is disabled or is active and does not detect a BOR event during Deep Sleep
RELEASE: I/O Pin State Deep Sleep Release bit
1 = I/O pins and SOSC maintain their states following exit from Deep Sleep, regardless of their LAT
0 = I/O pins and SOSC are released from their Deep Sleep states. The pin state is controlled by the
and TRIS configuration
LAT and TRIS configurations, and the SOSCEN bit.
U-0
U-0
—
—
DSCON: DEEP SLEEP CONTROL REGISTER
W = Writable bit
‘1’ = Bit is set
HS = Hardware Settable bit
U-0
U-0
—
—
(1)
PIC24FJ64GB004 FAMILY
U-0
U-0
—
—
(1,2,3)
C = Clearable bit
‘0’ = Bit is cleared
HCS = Hardware Clearable/Settable bit
U-0
U-0
—
—
(1,2)
U-0
U-0
—
—
U = Unimplemented, read as ‘0’
x = Bit is unknown
DSBOR
R/W-0, HCS
U-0
—
(1,2,3)
DS39940D-page 123
RELEASE
R/C-0, HS
U-0
—
(1,2)
bit 8
bit 0