PIC24FJ64GB002-I/ML Microchip Technology, PIC24FJ64GB002-I/ML Datasheet - Page 208

• Manufacturer Part Number: PIC24FJ64GB002-I/ML
• Description: IC MCU 16BIT 64KB FLASH 28QFN
• Manufacturer: Microchip Technology
• Series: PIC® XLP™ 24Fr

Specifications of PIC24FJ64GB002-I/ML

• Program Memory Type: FLASH
• Program Memory Size: 64KB (22K x 24)
• Package / Case: 28-VQFN Exposed Pad, 28-HVQFN, 28-SQFN, 28-DHVQFN
• Core Processor: PIC
• Core Size: 16-Bit
• Speed: 32MHz
• Connectivity: I²C, IrDA, SPI, UART/USART, USB OTG
• Peripherals: Brown-out Detect/Reset, LVD, POR, PWM, WDT
• Number Of I /o: 19
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 2 V ~ 3.6 V
• Data Converters: A/D 9x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Processor Series: PIC24FJ
• Core: PIC
• Data Bus Width: 16 bit
• Data Ram Size: 8 KB
• Interface Type: I2C/IrDA/SPI/UART
• Maximum Clock Frequency: 32 MHz
• Number Of Programmable I/os: 19
• Number Of Timers: 5
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: 52713-733, 52714-737, 53276-922, EWDSPIC
• Development Tools By Supplier: PG164130, DV164035, DV244005, DV164005, PG164120, DM240001, DM240011
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 9-ch x 10-bit
• Controller Family/series: PIC24
• Ram Memory Size: 8KB
• Cpu Speed: 32MHz
• No. Of Timers: 5
• Embedded Interface Type: I2C, LIN, SPI, UART, USB
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

PIC24FJ64GB004 FAMILY
18.4.2
1.
2.
3.
4.
18.4.3
1.
2.
3.
4.
DS39940D-page 208
Attach to a USB host and enumerate as described
in Chapter 9 of the USB 2.0 specification.
Create a data buffer, and populate it with the
data to send to the host.
In the appropriate (EVEN or ODD) Tx BD for the
desired endpoint:
a)
b)
c)
When the USB module receives an IN token, it
automatically transmits the data in the buffer.
Upon completion, the module updates the status
register (BDnSTAT) and sets the Transfer
Complete Interrupt Flag, TRNIF (U1IR<3>).
Attach to a USB host and enumerate as described
in Chapter 9 of the USB 2.0 specification.
Create a data buffer with the amount of data you
are expecting from the host.
In the appropriate (EVEN or ODD) Tx BD for the
desired endpoint:
a)
b)
c)
When the USB module receives an OUT token,
it automatically receives the data sent by the
host to the buffer. Upon completion, the module
updates the status register (BDnSTAT) and sets
the Transfer Complete Interrupt Flag, TRNIF
(U1IR<3>).
Set up the status register (BDnSTAT) with
the correct data toggle (DATA0/1) value and
the byte count of the data buffer.
Set up the address register (BDnADR) with
the starting address of the data buffer.
Set the UOWN bit of the status register to
‘1’.
Set up the status register (BDnSTAT) with
the correct data toggle (DATA0/1) value and
the byte count of the data buffer.
Set up the address register (BDnADR) with
the starting address of the data buffer.
Set the UOWN bit of the status register to
‘1’.
RECEIVING AN IN TOKEN IN
DEVICE MODE
RECEIVING AN OUT TOKEN IN
DEVICE MODE
Endpoint 0 control register (U1EP0) and buffer
descriptors.
18.5
The following sections describe how to perform common
Host mode tasks. In Host mode, USB transfers are
invoked explicitly by the host software. The host soft-
ware is responsible for the Acknowledge portion of the
transfer. Also, all transfers are performed using the
18.5.1
1.
2.
3.
4.
5.
6.
7.
8.
9.
10. Perform enumeration as described by Chapter 9
Enable Host mode by setting the HOSTEN bit
(U1CON<3>). This causes the Host mode
control bits in other USB OTG registers to
become available.
Enable the D+ and D- pull-down resistors by set-
ting
(U1OTGCON<5:4>). Disable the D+ and D-
pull-up resistors by clearing DPPULUP and
DMPULUP (U1OTGCON<7:6>).
At this point, SOF generation begins with the
SOF counter loaded with 12,000. Eliminate
noise on the USB by clearing the SOFEN bit
(U1CON<0>) to disable Start-of-Frame packet
generation.
Enable the device attached interrupt by setting
ATTACHIE (U1IE<6>).
Wait
(U1IR<6> = 1). This is signaled by the USB
device changing the state of D+ or D- from ‘0’
to ‘1’ (SE0 to J state). After it occurs, wait
100 ms for the device power to stabilize.
Check the state of the JSTATE and SE0 bits in
U1CON. If the JSTATE bit (U1CON<7>) is ‘0’,
the connecting device is low speed. If the con-
necting device is low speed, set the low
LSPDEN and LSPD bits (U1ADDR<7> and
U1EP0<7>) to enable low-speed operation.
Reset the USB device by setting the USBRST
bit (U1CON<4>) for at least 50 ms, sending
Reset signaling on the bus. After 50 ms,
terminate the Reset by clearing USBRST.
To keep the connected device from going into
suspend, enable SOF packet generation to keep
by setting the SOFEN bit.
Wait 10 ms for the device to recover from Reset.
of the USB 2.0 specification.
Host Mode Operation
for
ENABLE HOST MODE AND
DISCOVER A CONNECTED DEVICE
DPPULDWN
the
device
 2010 Microchip Technology Inc.
and
attached
DMPULDWN
interrupt