ATMEGA3290P-20AU Atmel, ATMEGA3290P-20AU Datasheet - Page 189
ATMEGA3290P-20AU
Manufacturer Part Number
ATMEGA3290P-20AU
Description
IC MCU 32K 4X40 LCD CTRL 100TQFP
Manufacturer
Atmel
Series
AVR® ATmegar
Specifications of ATMEGA3290P-20AU
Core Processor
AVR
Core Size
8-Bit
Speed
20MHz
Connectivity
SPI, UART/USART, USI
Peripherals
Brown-out Detect/Reset, LCD, POR, PWM, WDT
Number Of I /o
69
Program Memory Size
32KB (16K x 16)
Program Memory Type
FLASH
Eeprom Size
1K x 8
Ram Size
2K x 8
Voltage - Supply (vcc/vdd)
2.7 V ~ 5.5 V
Data Converters
A/D 8x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
100-TQFP, 100-VQFP
Processor Series
ATMEGA32x
Core
AVR8
Data Bus Width
8 bit
Data Ram Size
2 KB
Interface Type
SPI, USART, USI
Maximum Clock Frequency
20 MHz
Number Of Programmable I/os
69
Number Of Timers
3
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
3rd Party Development Tools
EWAVR, EWAVR-BL
Development Tools By Supplier
ATAVRDRAGON, ATSTK500, ATSTK600, ATAVRISP2, ATAVRONEKIT
Minimum Operating Temperature
- 40 C
On-chip Adc
10 bit, 8 Channel
Package
100TQFP
Device Core
AVR
Family Name
ATmega
Maximum Speed
20 MHz
Operating Supply Voltage
3.3|5 V
Controller Family/series
AVR MEGA
No. Of I/o's
69
Eeprom Memory Size
1KB
Ram Memory Size
2KB
Cpu Speed
20MHz
Rohs Compliant
Yes
For Use With
ATSTK600-TQFP100 - STK600 SOCKET/ADAPTER 100-TQFP770-1007 - ISP 4PORT ATMEL AVR MCU SPI/JTAG770-1005 - ISP 4PORT FOR ATMEL AVR MCU JTAG770-1004 - ISP 4PORT FOR ATMEL AVR MCU SPIATAVRISP2 - PROGRAMMER AVR IN SYSTEMATSTK504 - STARTER KIT AVR EXP MOD 100P LCDATJTAGICE2 - AVR ON-CHIP D-BUG SYSTEM
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Other names
ATMEGA3290P-16AU
ATMEGA3290P-16AU
ATMEGA3290P-16AU
Available stocks
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Manufacturer
Quantity
Price
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19.10 Register Description
19.10.1
19.10.2
8021G–AVR–03/11
UDRn – USART I/O Data Register n
UCSRnA – USART Control and Status Register n A
The USART Transmit Data Buffer Register and USART Receive Data Buffer Registers share the
same I/O address referred to as USART Data Register or UDRn. The Transmit Data Buffer Reg-
ister (TXB) will be the destination for data written to the UDRn Register location. Reading the
UDRn Register location will return the contents of the Receive Data Buffer Register (RXB).
For 5-, 6-, or 7-bit characters the upper unused bits will be ignored by the Transmitter and set to
zero by the Receiver.
The transmit buffer can only be written when the UDREn Flag in the UCSRnA Register is set.
Data written to UDRn when the UDREn Flag is not set, will be ignored by the USART Transmit-
ter. When data is written to the transmit buffer, and the Transmitter is enabled, the Transmitter
will load the data into the Transmit Shift Register when the Shift Register is empty. Then the
data will be serially transmitted on the TxD pin.
The receive buffer consists of a two level FIFO. The FIFO will change its state whenever the
receive buffer is accessed. Due to this behavior of the receive buffer, do not use Read-Modify-
Write instructions (SBI and CBI) on this location. Be careful when using bit test instructions
(SBIC and SBIS), since these also will change the state of the FIFO.
• Bit 7 – RXCn: USART Receive Complete
This flag bit is set when there are unread data in the receive buffer and cleared when the receive
buffer is empty (i.e., does not contain any unread data). If the Receiver is disabled, the receive
buffer will be flushed and consequently the RXCn bit will become zero. The RXCn Flag can be
used to generate a Receive Complete interrupt (see description of the RXCIEn bit).
• Bit 6 – TXCn: USART Transmit Complete
This flag bit is set when the entire frame in the Transmit Shift Register has been shifted out and
there are no new data currently present in the transmit buffer (UDRn). The TXCn Flag bit is auto-
matically cleared when a transmit complete interrupt is executed, or it can be cleared by writing
a one to its bit location. The TXCn Flag can generate a Transmit Complete interrupt (see
description of the TXCIEn bit).
Bit
Read/Write
Initial Value
Bit
Read/Write
Initial Value
RXCn
R/W
R
7
0
7
0
TXCn
R/W
R/W
6
0
6
0
UDREn
R/W
5
0
R
5
1
R/W
FEn
4
0
R
RXBn[7:0]
4
0
TXBn[7:0]
R/W
DORn
3
0
R
3
0
ATmega329P/3290P
R/W
2
0
UPEn
R
2
0
R/W
1
0
U2Xn
R/W
1
0
R/W
0
0
MPCMn
R/W
0
0
UDRn (Read)
UDRn (Write)
UCSRnA
189
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