DSPIC30F2020-20E/SP Microchip Technology, DSPIC30F2020-20E/SP Datasheet - Page 8
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DSPIC30F2020-20E/SP
Manufacturer Part Number
DSPIC30F2020-20E/SP
Description
IC DSPIC MCU/DSP 12K 28DIP
Manufacturer
Microchip Technology
Series
dsPIC™ 30Fr
Datasheets
1.AC164335.pdf
(286 pages)
2.DM300023.pdf
(22 pages)
3.DM300023.pdf
(18 pages)
4.DSPIC30F2011-20ISO.pdf
(66 pages)
5.DSPIC30F2011-20IP.pdf
(26 pages)
6.DSPIC30F1010-30ISO.pdf
(26 pages)
7.DSPIC30F1010-30ISO.pdf
(50 pages)
Specifications of DSPIC30F2020-20E/SP
Core Processor
dsPIC
Core Size
16-Bit
Speed
20 MIPS
Connectivity
I²C, IrDA, LIN, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, POR, PWM, WDT
Number Of I /o
21
Program Memory Size
12KB (4K x 24)
Program Memory Type
FLASH
Ram Size
512 x 8
Voltage - Supply (vcc/vdd)
3 V ~ 5.5 V
Data Converters
A/D 8x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 125°C
Package / Case
28-DIP (0.300", 7.62mm)
Core Frequency
15MHz
Core Supply Voltage
5.5V
Embedded Interface Type
I2C, SPI, UART
No. Of I/o's
21
Flash Memory Size
12KB
Supply Voltage Range
3V To 5.5V
Package
28SPDIP
Device Core
dsPIC
Family Name
dsPIC30
Maximum Speed
20 MHz
Operating Supply Voltage
3.3|5 V
Data Bus Width
16 Bit
Number Of Programmable I/os
21
Interface Type
I2C/SPI/UART
On-chip Adc
8-chx10-bit
Number Of Timers
3
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
For Use With
DM300023 - KIT DEMO DSPICDEM SMPS BUCKDV164005 - KIT ICD2 SIMPLE SUIT W/USB CABLE
Eeprom Size
-
Lead Free Status / RoHS Status
Lead free / RoHS Compliant, Lead free / RoHS Compliant
dsPIC30F1010/202X
15. Module: Output Compare Module in PWM
16. Module: Output Compare Module
DS80319D-page 8
The output compare module will miss a compare
event when the current duty cycle register
(OCxRS) value is 0x0000 (0% duty cycle) and the
OCxRS register is updated with a value of 0x0001.
The compare event is missed only the first time a
value of 0x0001 is written to OCxRS, and the
PWM output remains low for one PWM period.
Subsequent PWM high and low times occur as
expected.
Work around
None. If the current OCxRS register value is
0x0000, avoid writing a value of 0x0001 to
OCxRS. Instead, write a value of 0x0002;
however, in this case the duty cycle will be slightly
different from the desired value.
When the Output Compare Module is operated in
the Dual Compare Match mode, a timer compare
match with the value in the OCxR register sets the
OCx output producing a rising edge on the OCx
pin. Then, when a timer compare match with the
value in the OCxRS register occurs, the OCx
output is reset producing a falling edge on the OCx
pin.
The above statement applies to all conditions
except when the difference between OCxR and
OCxRS is ‘1’. In this case, the Output Compare
module may miss the reset compare event, and
cause the OCx pin to remain continuously high.
This condition will remain until the difference
between values in the OCxR and OCxRS registers
is made greater than ‘1’.
Work around
Ensure in software that the difference between
values in OCxR and OCxRS registers is
maintained greater than ‘1’.
Mode
17. Module: SPI Module in Slave Select Mode
18. Module: SPI Module in Frame Master
Note:
Note:
The SPI module Slave Select functionality
(enabled by setting SSEN = 1) will not function
correctly. Whether the SSx pin (x = 1 or 2) is high
or low, the SPI data transfer will be completed and
an interrupt will be generated. This applies to the
dsPIC30F2023 device only.
Work around
Manually poll the SSx pin state in the SPI interrupt
by reading the associated PORT bit:
• If the PORT bit is ‘0’, then perform the required
• If the PORT bit is ‘1’, then clear the SPI
The SPI module will fail to generate frame
synchronization pulses when configured in the
Frame Master mode if the start of data is selected
to
synchronization pulse (FRMEN = 1, SPIFSD = 0).
However, the module functions correctly in Frame
Slave mode, and also in Frame Master mode if
FRMDLY = 0. This applies to the dsPIC30F2023
device only.
Work around
Manually drive the SSx pin (x = 1 or 2) high using
the associated PORT register, and then drive it low
after the required 1 bit-time pulse-width. This
operation needs to be performed when the
transmit buffer is written.
If FRMDLY = 0, no work around is needed.
data read/write.
interrupt flag (SPIxIF), perform a dummy read
of the SPIxBUF register, and return from the
Interrupt Service Routine.
coincide
The dsPIC30F1010/202X devices have
only one SPI. All references to x = 2 are
intended for software compatibility with
other dsPIC DSC devices.
The dsPIC30F1010/202X devices have
only one SPI. All references to x = 2 are
intended for software compatibility with
other dsPIC DSC devices.
Mode
with
© 2008 Microchip Technology Inc.
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