ATMEGA32L-8AUR Atmel, ATMEGA32L-8AUR Datasheet - Page 42
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ATMEGA32L-8AUR
Manufacturer Part Number
ATMEGA32L-8AUR
Description
MCU AVR 32K FLASH 8MHZ 44TQFP
Manufacturer
Atmel
Series
AVR® ATmegar
Specifications of ATMEGA32L-8AUR
Core Processor
AVR
Core Size
8-Bit
Speed
8MHz
Connectivity
I²C, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, POR, PWM, WDT
Number Of I /o
32
Program Memory Size
32KB (16K x 16)
Program Memory Type
FLASH
Eeprom Size
1K x 8
Ram Size
2K x 8
Voltage - Supply (vcc/vdd)
2.7 V ~ 5.5 V
Data Converters
A/D 8x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
*
Package
44TQFP
Device Core
AVR
Family Name
ATmega
Maximum Speed
8 MHz
Operating Supply Voltage
3.3|5 V
Data Bus Width
8 Bit
Number Of Programmable I/os
32
Interface Type
TWI/SPI/USART
On-chip Adc
8-chx10-bit
Number Of Timers
3
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
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Watchdog Timer
Control Register –
WDTCR
2503Q–AVR–02/11
• Bits [7:5] – Reserved Bits
These bits are reserved bits in the ATmega32 and will always read as zero.
• Bit 4 – WDTOE: Watchdog Turn-off Enable
This bit must be set when the WDE bit is written to logic zero. Otherwise, the Watchdog will not
be disabled. Once written to one, hardware will clear this bit after four clock cycles. Refer to the
description of the WDE bit for a Watchdog disable procedure.
• Bit 3 – WDE: Watchdog Enable
When the WDE is written to logic one, the Watchdog Timer is enabled, and if the WDE is written
to logic zero, the Watchdog Timer function is disabled. WDE can only be cleared if the WDTOE
bit has logic level one. To disable an enabled Watchdog Timer, the following procedure must be
followed:
1. In the same operation, write a logic one to WDTOE and WDE. A logic one must be writ-
2. Within the next four clock cycles, write a logic 0 to WDE. This disables the Watchdog.
• Bits [2:0] – WDP2, WDP1, WDP0: Watchdog Timer Prescaler 2, 1, and 0
The WDP2, WDP1, and WDP0 bits determine the Watchdog Timer prescaling when the Watch-
dog Timer is enabled. The different prescaling values and their corresponding Timeout Periods
are shown in
Table 17. Watchdog Timer Prescale Select
Bit
Read/Write
Initial Value
WDP2
0
0
0
0
1
1
1
1
ten to WDE even though it is set to one before the disable operation starts.
WDP1
0
0
1
1
0
0
1
1
Table
R
7
–
0
WDP0
17.
0
1
0
1
0
1
0
1
R
6
–
0
1,024K (1,048,576)
2,048K (2,097,152)
Oscillator Cycles
Number of WDT
128K (131,072)
256K (262,144)
512K (524,288)
16K (16,384)
32K (32,768)
64K (65,536)
R
5
–
0
WDTOE
R/W
4
0
WDE
R/W
3
0
Typical Time-out
at V
WDP2
17.1ms
34.3ms
68.5ms
R/W
CC
0.14s
0.27s
0.55s
2
0
1.1s
2.2s
= 3.0V
WDP1
R/W
1
0
Typical Time-out
ATmega32(L)
WDP0
at V
R/W
0
0
16.3ms
32.5ms
0.13 s
65ms
0.26s
0.52s
CC
1.0s
2.1s
= 5.0V
WDTCR
42
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