ATMEGA32L-8AUR Atmel, ATMEGA32L-8AUR Datasheet - Page 256

• Manufacturer Part Number: ATMEGA32L-8AUR
• Description: MCU AVR 32K FLASH 8MHZ 44TQFP
• Manufacturer: Atmel
• Series: AVR® ATmegar

Specifications of ATMEGA32L-8AUR

• Core Processor: AVR
• Core Size: 8-Bit
• Speed: 8MHz
• Connectivity: I²C, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, POR, PWM, WDT
• Number Of I /o: 32
• Program Memory Size: 32KB (16K x 16)
• Program Memory Type: FLASH
• Eeprom Size: 1K x 8
• Ram Size: 2K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 5.5 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Package: 44TQFP
• Device Core: AVR
• Family Name: ATmega
• Maximum Speed: 8 MHz
• Operating Supply Voltage: 3.3|5 V
• Data Bus Width: 8 Bit
• Number Of Programmable I/os: 32
• Interface Type: TWI/SPI/USART
• On-chip Adc: 8-chx10-bit
• Number Of Timers: 3
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Memory
Programming
Program And Data
Memory Lock Bits
2503Q–AVR–02/11
The ATmega32 provides six Lock bits which can be left unprogrammed (“1”) or can be pro-
grammed (“0”) to obtain the additional features listed in
erased to “1” with the Chip Erase command.
Table 102. Lock Bit Byte
Note:
Table 103. Lock Bit Protection Modes
BLB12
BLB11
BLB02
BLB01
LB2
LB1
BLB0 Mode
BLB1 Mode
LB Mode
Lock Bit Byte
1
2
3
1
2
3
4
Memory Lock Bits
1. “1” means unprogrammed, “0” means programmed
BLB02
BLB12
LB2
1
1
0
1
1
0
0
(2)
BLB01
BLB11
(1)
LB1
Bit No.
1
0
0
1
0
0
1
7
6
5
4
3
2
1
0
Protection Type
No memory lock features enabled.
Further programming of the Flash and EEPROM is
disabled in Parallel and SPI/JTAG Serial Programming
mode. The Fuse bits are locked in both Serial and Parallel
Programming mode.
Further programming and verification of the Flash and
EEPROM is disabled in Parallel and SPI/JTAG Serial
Programming mode. The Fuse bits are locked in both
Serial and Parallel Programming mode.
No restrictions for SPM or LPM accessing the Application
section.
SPM is not allowed to write to the Application section.
SPM is not allowed to write to the Application section, and
LPM executing from the Boot Loader section is not
allowed to read from the Application section. If interrupt
vectors are placed in the Boot Loader section, interrupts
are disabled while executing from the Application section.
LPM executing from the Boot Loader section is not
allowed to read from the Application section. If interrupt
vectors are placed in the Boot Loader section, interrupts
are disabled while executing from the Application section.
Description
–
–
Boot Lock bit
Boot Lock bit
Boot Lock bit
Boot Lock bit
Lock bit
Lock bit
(1)
Table
Default Value
1 (unprogrammed)
1 (unprogrammed)
1 (unprogrammed)
1 (unprogrammed)
1 (unprogrammed)
1 (unprogrammed)
1 (unprogrammed)
1 (unprogrammed)
103. The Lock bits can only be
(1)
ATmega32(L)
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