PIC24FJ256GA106T-I/PT Microchip Technology, PIC24FJ256GA106T-I/PT Datasheet - Page 14

• Manufacturer Part Number: PIC24FJ256GA106T-I/PT
• Description: IC PIC MCU FLASH 256K 64TQFP
• Manufacturer: Microchip Technology
• Series: PIC® 24Fr

Specifications of PIC24FJ256GA106T-I/PT

• Core Processor: PIC
• Core Size: 16-Bit
• Speed: 32MHz
• Connectivity: I²C, PMP, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, LVD, POR, PWM, WDT
• Number Of I /o: 53
• Program Memory Size: 256KB (85.5K x 24)
• Program Memory Type: FLASH
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 2 V ~ 3.6 V
• Data Converters: A/D 16x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 64-TFQFP
• Processor Series: PIC24FJ
• Core: PIC
• Data Bus Width: 16 bit
• Data Ram Size: 16 KB
• Interface Type: I2C, SPI, UART
• Maximum Clock Frequency: 32 MHz
• Number Of Programmable I/os: 53
• Number Of Timers: 5
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: 52713-733, 52714-737, 53276-922, EWDSPIC
• Development Tools By Supplier: PG164130, DV164035, DV244005, DV164005, PG164120, DM240001, DM240011
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 10 bit, 16 Channel
• A/d Bit Size: 10 bit
• A/d Channels Available: 16
• Height: 1 mm
• Length: 10 mm
• Supply Voltage (max): 3.6 V
• Supply Voltage (min): 2 V
• Width: 10 mm
• For Use With: MA240015 - BOARD MCV PIM FOR 24F256GADM240011 - KIT STARTER MPLAB FOR PIC24F MCUAC164327 - MODULE SKT FOR 64TQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details
• Other names: PIC24FJ256GA106T-I/PTTR

PIC24FJXXXDA1/DA2/GB2/GA3
3.0
ICSP mode is a special programming protocol that
allows you to read and write to the memory of
PIC24FJXXXDA1/DA2/GB2/GA3 devices. The ICSP
mode is the most direct method used to program the
device; however, Enhanced ICSP is faster. ICSP mode
also has the ability to read the contents of executive
memory to determine if the programming executive is
present. This capability is accomplished by applying
control codes and instructions, serially to the device,
using pins, PGECx and PGEDx.
In ICSP mode, the system clock is taken from the
PGECx pin, regardless of the device’s oscillator Con-
figuration bits. All instructions are shifted serially into an
internal buffer, then loaded into the Instruction Register
(IR) and executed. No program fetching occurs from
internal memory. Instructions are fed in 24 bits at a
time. PGEDx is used to shift data in and PGECx is used
as both the serial shift clock and the CPU execution
clock.
3.1
See
programming process. After entering ICSP mode, the
first action is to Chip Erase the device. Next, the code
memory is programmed, followed by the device
Configuration registers. Code memory (including the
Configuration registers) is then verified to ensure that
programming was successful. Then, the code-protect
Configuration bits are programmed, if required.
DS39970B-page 14
Note:
Figure 3-1
DEVICE PROGRAMMING – ICSP
Overview of the Programming
Process
During ICSP operation, the operating
frequency of PGECx must not exceed
10 MHz.
for high-level overview of the
3.2
Upon entry into ICSP mode, the CPU is Idle. Execution
of the CPU is governed by an internal state machine. A
4-bit control code is clocked in using PGECx and
PGEDx and this control code is used to command the
CPU (see
The SIX control code is used to send instructions to the
CPU for execution and the REGOUT control code is
used to read data out of the device via the VISI register.
TABLE 3-1:
FIGURE 3-1:
Control Code
0010-1111
0000
0001
4-Bit
ICSP Operation
Table
Program Configuration Bits
Verify Configuration Bits
3-1).
Mnemonic
REGOUT Shift out the VISI
CPU CONTROL CODES IN
ICSP™ MODE
Program Memory
SIX
N/A
Verify Program
Enter ICSP™
Perform Chip
HIGH-LEVEL ICSP™
PROGRAMMING FLOW
Exit ICSP
 2010 Microchip Technology Inc.
Erase
Start
End
Shift in 24-bit instruction
and execute.
(0784h) register.
Reserved.
Description